公开(公告)号：US10402533B1

公开(公告)日：2019-09-03

申请号：US15691631

申请日：2017-08-30

Applicant: Cadence Design Systems, Inc.

Inventor： William Robert Reece ,  Yi-Xiao Ding ,  Thomas Andrew Newton ,  Charles Jay Alpert ,  Zhuo Li

IPC: G06F17/50

Abstract: Systems, methods, media, and other such embodiments are described for placement of cells in a multi-level routing tree, where placement of a mid-level parent node between a grandparent node and a set of child nodes is not set. One embodiment involves generating a first routing subregion between a first set of child nodes associated with a first grandparent node and a first connecting route from the first routing subregion to the first grandparent node, which together are set as a first routing region comprising the first routing subregion and the first connecting route. Sampling points are selected along the first routing region, and for each sampling point a set of operating values associated with the sampling point is calculated. A position for the parent node is selected based on the operating values for the sampling points.

公开(公告)号：US10289795B1

公开(公告)日：2019-05-14

申请号：US15683659

申请日：2017-08-22

Applicant: Cadence Design Systems, Inc.

Inventor： Jhih-Rong Gao ,  Thomas Andrew Newton ,  Derong Liu ,  Mehmet Can Yildiz ,  Charles Jay Alpert ,  Zhuo Li

IPC: G06F17/50

Abstract: Systems, methods, media, and other such embodiments described herein relate to generation of routing trees. One embodiment involves accessing a circuit design comprising a source, a plurality of sinks, and a skew threshold associated with the source and the plurality of sinks. An initial routing tree is generated between the source and the plurality of sinks, and then a first intermediate point is identified between the source and the plurality of sinks. The first intermediate point may be identified based on a median location of all sinks of the plurality of sinks, or other criteria. The first intermediate point is then used for an updated routing tree. In some embodiments, a process proceeds iteratively until the skew threshold is reached or a maximum wire length is exceeded.

公开(公告)号：US10282506B1

公开(公告)日：2019-05-07

申请号：US15688725

申请日：2017-08-28

Applicant: Cadence Design Systems, Inc.

Inventor： Dirk Meyer ,  Zhuo Li ,  Charles Jay Alpert

IPC: G06F1/10 ,  G06F17/50

Abstract: Systems, methods, media, and other such embodiments described herein relate to generation of clock routing trees. One embodiment involves accessing a circuit design and a clock tree hierarchy input indicating a nested list of partition or sink groups, each group of the nested list of groups comprising one or more clock tree elements of a plurality of clock tree elements from the circuit design. A routing topology associated with a source and a plurality of sinks are determined based on an ordering within the nested list of partition groups. These routing directions are used in synthesizing a clock tree for the circuit design. In additional embodiments, the clock tree hierarchy input provides clustering information, port placement for connections between partition groups of the clock tree, and parameters describing limitations or criteria for individual partition groups.

公开(公告)号：US10198551B1

公开(公告)日：2019-02-05

申请号：US15680646

申请日：2017-08-18

Applicant: Cadence Design Systems, Inc.

Inventor： Amin Farshidi ,  Zhuo Li ,  Charles Jay Alpert ,  William Robert Reece

IPC: G06F17/50

Abstract: Systems, methods, media, and other such embodiments described herein relate to trimming cell lists prior to generation of a routing tree for a circuit design. One embodiment involves accessing a cell library including cell data and a cell list for a plurality of cells. Specialized delay cells are removed from the cell list, and remaining cells are analyzed to identify a set of cell characteristics. Cells are then trimmed from the cell list based on comparisons between the cell characteristics of the remaining cells. If certain cells are sufficiently similar, secondary characteristics can be used to further trim the cell list. The trimmed cell list can then be used to generate a routing tree for the circuit design according to associated design criteria.