公开(公告)号：US20090006923A1

公开(公告)日：2009-01-01

申请号：US11768527

申请日：2007-06-26

申请人： Alan G. Gara ,  Dong Chen ,  Philip Heidelberger ,  Martin Ohmacht

发明人： Alan G. Gara ,  Dong Chen ,  Philip Heidelberger ,  Martin Ohmacht

IPC分类号： H03M13/00

CPC分类号： G06F11/1076 ,  G06F11/1064 ,  G06F2212/403 ,  H03M1/0687 ,  H03M13/13 ,  H03M13/2707 ,  H03M13/271 ,  H03M13/29 ,  H03M13/616

摘要： A method and system are disclosed for providing combined error code protection and subgroup parity protection for a given group of n bits. The method comprises the steps of identifying a number, m, of redundant bits for said error protection; and constructing a matrix P, wherein multiplying said given group of n bits with P produces m redundant error correction code (ECC) protection bits, and two columns of P provide parity protection for subgroups of said given group of n bits. In the preferred embodiment of the invention, the matrix P is constructed by generating permutations of m bit wide vectors with three or more, but an odd number of, elements with value one and the other elements with value zero; and assigning said vectors to rows of the matrix P.

摘要翻译： 公开了用于为给定的n位组提供组合的错误代码保护和子组奇偶校验保护的方法和系统。 该方法包括以下步骤：识别用于所述错误保护的冗余位的数量m; 并且构造矩阵P，其中将所述给定的n个比特组与P相乘产生m个冗余纠错码（ECC）保护比特，并且两列P为所述给定组n比特的子组提供奇偶校验保护。 在本发明的优选实施例中，矩阵P是通过产生具有三个或更多个奇数个元素的m位宽向量的排列而构成的，其中值为1的元素和其他元素的值为零; 并将所述向量分配给矩阵P的行。

公开(公告)号：US07380071B2

公开(公告)日：2008-05-27

申请号：US11093127

申请日：2005-03-29

申请人： Matthias A. Blumrich ,  Dong Chen ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk I. Hoenicke ,  Martin Ohmacht ,  Valentina Salapura ,  Pavlos M. Vranas

发明人： Matthias A. Blumrich ,  Dong Chen ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk I. Hoenicke ,  Martin Ohmacht ,  Valentina Salapura ,  Pavlos M. Vranas

IPC分类号： G06F13/28 ,  G06F12/00

CPC分类号： G06F12/0831 ,  G06F12/0813 ,  Y02D10/13

摘要： A system and method for supporting cache coherency in a computing environment having multiple processing units, each unit having an associated cache memory system operatively coupled therewith. The system includes a plurality of interconnected snoop filter units, each snoop filter unit corresponding to and in communication with a respective processing unit, with each snoop filter unit comprising a plurality of devices for receiving asynchronous snoop requests from respective memory writing sources in the computing environment; and a point-to-point interconnect comprising communication links for directly connecting memory writing sources to corresponding receiving devices; and, a plurality of parallel operating filter devices coupled in one-to-one correspondence with each receiving device for processing snoop requests received thereat and one of forwarding requests or preventing forwarding of requests to its associated processing unit. Each of the plurality of parallel operating filter devices comprises parallel operating sub-filter elements, each simultaneously receiving an identical snoop request and implementing one or more different snoop filter algorithms for determining those snoop requests for data that are determined not cached locally at the associated processing unit and preventing forwarding of those requests to the processor unit. In this manner, a number of snoop requests forwarded to a processing unit is reduced thereby increasing performance of the computing environment.

摘要翻译： 一种用于在具有多个处理单元的计算环境中支持高速缓存一致性的系统和方法，每个单元具有与其可操作地耦合的相关联的高速缓冲存储器系统。 该系统包括多个互连的窥探过滤器单元，每个窥探过滤器单元对应于相应处理单元并与其通信，每个窥探过滤器单元包括用于在计算环境中从相应存储器写入源接收异步窥探请求的多个设备 ; 以及包括用于将存储器写入源直接连接到对应的接收设备的通信链路的点对点互连; 以及与每个接收设备一一对应地耦合的多个并行操作过滤器设备，用于处理在其上接收的窥探请求，并且转发请求之一或者阻止将请求转发到其相关联的处理单元。 多个并行操作过滤器装置中的每一个包括并行操作子滤波器元件，每个并行操作子滤波器元件同时接收相同的窥探请求，并且实现一个或多个不同的窥探滤波器算法，用于确定对于在相关处理中本地未被缓存的数据被确定的窥探请求 并且防止将这些请求转发到处理器单元。 以这种方式，减少了转发到处理单元的多个窥探请求，从而增加了计算环境的性能。

公开(公告)号：US07330996B2

公开(公告)日：2008-02-12

申请号：US10468990

申请日：2002-02-25

申请人： Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Burkhard D. Steinmacher-Burow

发明人： Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Burkhard D. Steinmacher-Burow

IPC分类号： G06F11/00 ,  G06F11/20

CPC分类号： H05K7/20836 ,  F24F11/77 ,  G06F9/52 ,  G06F9/526 ,  G06F15/17381 ,  G06F17/142 ,  G09G5/008 ,  H04L7/0338

摘要： A method for maintaining full performance of a file system in the presence of a failure is provided. The file system having N storage devices, where N is an integer greater than zero and N primary file servers where each file server is operatively connected to a corresponding storage device for accessing files therein. The file system further having a secondary file server operatively connected to at least one of the N storage devices. The method including: switching the connection of one of the N storage devices to the secondary file server upon a failure of one of the N primary file servers; and switching the connections of one or more of the remaining storage devices to a primary file server other than the failed file server as necessary so as to prevent a loss in performance and to provide each storage device with an operating file server.

摘要翻译： 提供了在出现故障的情况下维持文件系统的完整性能的方法。 具有N个存储设备的文件系统，其中N是大于零的整数，N个主文件服务器，其中每个文件服务器可操作地连接到用于访问其中的文件的相应存储设备。 所述文件系统还具有可操作地连接到所述N个存储设备中的至少一个的辅助文件服务器。 该方法包括：在N个主要文件服务器之一发生故障时，将N个存储设备之一的连接切换到次要文件服务器; 并且根据需要将一个或多个剩余存储设备的连接切换到除故障文件服务器之外的主文件服务器，以防止性能损失并向每个存储设备提供操作文件服务器。

公开(公告)号：US07174434B2

公开(公告)日：2007-02-06

申请号：US10468994

申请日：2002-02-25

申请人： Matthias A. Blumrich ,  Dong Chen ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk Hoenicke ,  Martin Ohmacht ,  Burkhard D. Steinmacher-Burow ,  Todd E. Takken ,  Pavlos M. Vranas

发明人： Matthias A. Blumrich ,  Dong Chen ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk Hoenicke ,  Martin Ohmacht ,  Burkhard D. Steinmacher-Burow ,  Todd E. Takken ,  Pavlos M. Vranas

IPC分类号： G06F12/12

CPC分类号： G06F9/52

摘要： A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive.

摘要翻译： 与弱有序的多处理器系统相关联地提供低延迟存储器系统访问。 多处理器中的每个处理器共享资源，并且每个共享资源在锁定设备内具有关联的锁，其提供对多处理器中的多个处理器之间的同步的支持以及资源的有序共享。 当处理器拥有与该资源相关联的锁定时，处理器仅具有访问资源的权限，并且处理器拥有锁的尝试仅需要单个加载操作，而不是传统的原子负载后跟存储，使得处理器 只执行读取操作，并且硬件锁定装置执行后续的写入操作而不是处理器。 还公开了用于非连续数据结构的简单预取。 重新定义存储器线，使得除了正常的物理存储器数据之外，每行包括足够大的指针以指向存储器中的任何其他行，其中指针用于确定要预取的存储器行而不是一些其它预测 算法。 这使得硬件能够有效地预取不连续但重复的存储器访问模式。

公开(公告)号：US20060101104A1

公开(公告)日：2006-05-11

申请号：US10963101

申请日：2004-10-12

申请人： Gyan Bhanot ,  Alan Gara ,  Philip Heidelberger ,  Eoin Lawless ,  James Sexton ,  Robert Walkup

发明人： Gyan Bhanot ,  Alan Gara ,  Philip Heidelberger ,  Eoin Lawless ,  James Sexton ,  Robert Walkup

IPC分类号： G06F1/16

CPC分类号： G06F9/5066

摘要： A general computer-implement method and apparatus to optimize problem layout on a massively parallel supercomputer is described. The method takes as input the communication matrix of an arbitrary problem in the form of an array whose entries C(i, j) are the amount to data communicated from domain i to domain j. Given C(i, j), first implement a heuristic map is implemented which attempts sequentially to map a domain and its communications neighbors either to the same supercomputer node or to near-neighbor nodes on the supercomputer torus while keeping the number of domains mapped to a supercomputer node constant (as much as possible). Next a Markov Chain of maps is generated from the initial map using Monte Carlo simulation with Free Energy (cost function) F=Σi,jC(i,j)H(i,j)—where H(i,j) is the smallest number of hops on the supercomputer torus between domain i and domain j. On the cases tested, found was that the method produces good mappings and has the potential to be used as a general layout optimization tool for parallel codes. At the moment, the serial code implemented to test the method is un-optimized so that computation time to find the optimum map can be several hours on a typical PC. For production implementation, good parallel code for our algorithm would be required which could itself be implemented on supercomputer.

摘要翻译： 描述了在大型并行超级计算机上优化问题布局的通用计算机实现方法和装置。 该方法采用数组形式的任意问题的通信矩阵作为输入，其条目C（i，j）是从域i到域j传送的数据量。 给定C（i，j），首先实现启发式映射，其尝试顺序地将域及其通信邻居映射到超级计算机节点或超级计算机环面上的近邻节点，同时保持域的数量映射到 超级计算机节点常数（尽可能多）。 接下来，使用具有自由能量（成本函数）的蒙特卡罗模拟，从初始映射生成马尔可夫链映射，其中F =Σi，j C（i，j）H（i，j） H（i，j）是域i和域j之间的超级计算机环面上的最小跳数。 在测试的情况下，发现该方法产生良好的映射，并且有可能被用作并行代码的通用布局优化工具。 此时，实现测试方法的序列号未优化，以便在典型的PC上找到最佳映射的计算时间可以为几个小时。 对于生产实现，将需要我们的算法的良好的并行代码，这本身可以在超级计算机上实现。

公开(公告)号：US07039769B2

公开(公告)日：2006-05-02

申请号：US10158534

申请日：2002-05-30

申请人： Vittorio Castelli ,  Peter A. Franaszek ,  Philip Heidelberger ,  John Timothy Robinson

发明人： Vittorio Castelli ,  Peter A. Franaszek ,  Philip Heidelberger ,  John Timothy Robinson

IPC分类号： G06F12/06

CPC分类号： G06F12/0284 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1458 ,  G06F2212/401

摘要： In a computer system in which a plurality of hosts is connected through an interconnection network, an apparatus coupled to the interconnection network for allowing the plurality of hosts to share a collection of memory sectors, the memory sectors storing compressed data, is provided. The apparatus includes a network adapter for coupling the apparatus to the interconnection network; a memory for storing the collection of memory sectors; and control logic for managing the memory, the control logic including a memory compressor/decompressor. The memory further includes a directory for translating real addresses of at least one host to an address in the apparatus. A method for managing a number of memory sectors used by each host and a method for translating a real address specified by at least one host into a real address of the apparatus is also provided.

公开(公告)号：US07024512B1

公开(公告)日：2006-04-04

申请号：US09021333

申请日：1998-02-10

申请人： Peter Anthony Franaszek ,  Philip Heidelberger

发明人： Peter Anthony Franaszek ,  Philip Heidelberger

IPC分类号： G06F12/00 ,  G06F9/00

CPC分类号： G06F12/023 ,  G06F12/08 ,  G06F2212/401 ,  Y10S707/99942

摘要： An improved method, system, and a computer program storage device (e.g., including software embodied on a magnetic, electrical, optical, or other storage device) for management of compressed main memory allocation and utilization which can avoid system abends or inefficient operation that would otherwise result. One feature reduces (and ultimately eliminates) all unessential processing as the amount of available storage decreases to a point low enough to threaten a system abend. In another example, the amount of current memory usage is determined as well as one or more of: an estimate of an amount of allocated but unused memory; a determination of the amount of memory required for outstanding I/O requests. The compressed memory is managed as a function of the current memory usage and one or more of the other measured or estimated quantities. The compressed memory can be managed by maintaining a set of dynamic thresholds; estimating the amount of storage that can easily be freed (used but available) and the amount of storage that is committed (allocated but unused). The estimate of committed storage can include: the current storage utilization; and an estimate of storage committed to new pages (based on the number of new pages granted), the times at which this was done, the estimated compression ratio, and estimates of residency times in the cache.

摘要翻译： 改进的方法，系统和计算机程序存储设备（例如，包括在磁性，电气，光学或其他存储设备上实现的软件），用于管理压缩的主存储器分配和利用，其可以避免系统退出或低效的操作， 否则结果。 一个功能减少（并最终消除）所有不必要的处理，因为可用存储空间的数量减少到足以威胁系统退出的程度。 在另一示例中，确定当前存储器使用量，以及以下中的一个或多个：已分配但未使用的存储器的量的估计; 确定未完成的I / O请求所需的内存量。 根据当前内存使用情况和一个或多个其他测量或估计的数量来管理压缩存储器。 可以通过维护一组动态阈值来管理压缩存储器; 估计可以轻松释放（已用但可用）的存储量和已提交（已分配但未使用）的存储量。 承诺存储的估计可以包括：当前的存储利用率; 以及对新页面的存储量的估计（基于授予的新页面数量），完成的时间，估计的压缩率以及高速缓存中的驻留时间的估计。

公开(公告)号：US06381586B1

公开(公告)日：2002-04-30

申请号：US09209245

申请日：1998-12-10

申请人： Paul Glasserman ,  Philip Heidelberger ,  Nayyar P. Shahabuddin

发明人： Paul Glasserman ,  Philip Heidelberger ,  Nayyar P. Shahabuddin

IPC分类号： G06F1760

CPC分类号： G06F17/18 ,  G06Q40/00 ,  G06Q40/04 ,  G06Q40/06

摘要： A computer implemented method prices derivative securities (for example, options) by selecting an importance sampling (IS) distribution and combining the chosen IS distribution with stratified sampling. The process consists of the steps of choosing an importance sampling distribution and combining the chosen importance sampling with stratification or Quasi-Monte Carlo (QMC) simulation. In the first step, an importance sampling distribution is chosen. In the second step, the chosen importance sampling is combined with stratification or Quasi-Monte Carlo sequencing. The pricing of many types of securities reduces to one of estimating an expectation of a real-valued function of some random variables.

摘要翻译： 计算机实施的方法通过选择重要性抽样（IS）分布并将选择的IS分布与分层采样相结合来定价衍生证券（例如，期权）。 该过程包括以下步骤：选择重要性抽样分布，并将选择的重要性抽样与分层或准蒙特卡罗（QMC）模拟相结合。 在第一步中，选择重要性抽样分布。 在第二步中，选择的重要性抽样与分层或准蒙特卡罗测序相结合。 许多类型的证券的定价减少到估计一些随机变量的实值函数的期望值之一。

公开(公告)号：US10152450B2

公开(公告)日：2018-12-11

申请号：US13584323

申请日：2012-08-13

申请人： Dong Chen ,  Noel A. Eisley ,  Philip Heidelberger ,  James A. Kahle ,  Fabrizio Petrini ,  Robert M. Senger ,  Burkhard Steinmacher-Burow ,  Yutaka Sugawara

发明人： Dong Chen ,  Noel A. Eisley ,  Philip Heidelberger ,  James A. Kahle ,  Fabrizio Petrini ,  Robert M. Senger ,  Burkhard Steinmacher-Burow ,  Yutaka Sugawara

IPC分类号： G06F15/167 ,  G06F15/173 ,  G06F9/54 ,  H04L29/06 ,  H04L29/08

摘要： According to one embodiment of the present invention, a system for operating memory includes a first node coupled to a second node by a network, the system configured to perform a method including receiving the remote transaction message from the second node in a processing element in the first node via the network, wherein the remote transaction message bypasses a main processor in the first node as it is transmitted to the processing element. In addition, the method includes accessing, by the processing element, data from a location in a memory in the first node based on the remote transaction message, and performing, by the processing element, computations based on the data and the remote transaction message.

公开(公告)号：US09077616B2

公开(公告)日：2015-07-07

申请号：US13569789

申请日：2012-08-08

申请人： Dong Chen ,  Paul W. Coteus ,  Noel A. Eisley ,  Philip Heidelberger ,  Robert M. Senger ,  Yutaka Sugawara

发明人： Dong Chen ,  Paul W. Coteus ,  Noel A. Eisley ,  Philip Heidelberger ,  Robert M. Senger ,  Yutaka Sugawara

IPC分类号： H04L12/24 ,  H04L12/715

CPC分类号： H04L41/0663 ,  H04L41/12 ,  H04L41/145 ,  H04L45/04

摘要： According to one embodiment of the present invention, a system for network communication includes an M dimensional grid of node groups, each node group including N nodes, wherein M is greater than or equal to one and N is greater than one and each node comprises a router and intra-group links directly connecting each node in each node group to every other node in the node group. In addition, the system includes inter-group links directly connecting each node in each node group to a node in each neighboring node group in the M dimensional grid.

摘要翻译： 根据本发明的一个实施例，一种用于网络通信的系统包括节点组的M维网格，每个节点组包括N个节点，其中M大于或等于1，并且N大于1，并且每个节点包括 路由器和组内链路，将每个节点组中的每个节点直接连接到节点组中的每个其他节点。 此外，该系统包括将每个节点组中的每个节点直接连接到M维网格中的每个相邻节点组中的节点的组间链路。