公开(公告)号：US08629058B2

公开(公告)日：2014-01-14

申请号：US13595835

申请日：2012-08-27

Applicant: Shau-Lin Shue ,  Cheng-Lin Huang ,  Ching-Hua Hsieh

Inventor： Shau-Lin Shue ,  Cheng-Lin Huang ,  Ching-Hua Hsieh

IPC: H01L21/4763

CPC classification number: H01L23/5226 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for forming a via structure are provided. The method includes depositing a first-layer conductive line over a semiconductor substrate, forming a dielectric layer over the first-layer conductive line, forming a via opening in the dielectric layer and exposing the first-layer conductive line in the via opening, forming a recess portion in the first-layer conductive line, and filling the via opening to form a via extending through the dielectric layer to the first-layer conductive line. The via has a substantially tapered profile and substantially extends into the recess in the first-layer conductive line.

Abstract translation: 提供了形成通孔结构的方法。 该方法包括在半导体衬底上沉积第一层导电线，在第一层导电线上形成电介质层，在电介质层中形成通孔，并在通路孔中露出第一层导电线，形成 在第一层导电线中的凹陷部分，并且填充通孔开口以形成延伸通过介电层到第一层导电线的通孔。 通孔具有基本上锥形的轮廓并且基本上延伸到第一层导电线中的凹部中。

公开(公告)号：US08456009B2

公开(公告)日：2013-06-04

申请号：US12707969

申请日：2010-02-18

Applicant: Shu-Hui Su ,  Cheng-Lin Huang ,  Jiing-Feng Yang ,  Zhen-Cheng Wu ,  Ren-Guei Wu ,  Dian-Hau Chen ,  Yuh-Jier Mii

Inventor： Shu-Hui Su ,  Cheng-Lin Huang ,  Jiing-Feng Yang ,  Zhen-Cheng Wu ,  Ren-Guei Wu ,  Dian-Hau Chen ,  Yuh-Jier Mii

IPC: H01L29/40

CPC classification number: H01L23/5226 ,  H01L21/02203 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: A semiconductor structure includes a first metal-containing layer, a dielectric capping layer, a second metal-containing layer, and a conductive pad. The first metal-containing layer includes a set of metal structures, a dielectric filler disposed to occupy a portion of the first metal-containing layer, and an air-gap region defined by at least the set of metal structures and the dielectric filler and abutting at least a portion of the set of metal structures. The second metal-containing layer includes at least a via plug electrically connected to a portion of the set of metal structures. The conductive pad and the via plug do not overlap the air-gap region.

Abstract translation: 半导体结构包括第一含金属层，电介质覆盖层，第二含金属层和导电焊盘。 第一含金属层包括一组金属结构，设置成占据第一含金属层的一部分的介电填料，以及由至少一组金属结构和介电填料限定的气隙区，并邻接 该组金属结构的至少一部分。 第二含金属层至少包括与该组金属结构的一部分电连接的通孔塞。 导电焊盘和通孔插头不与气隙区域重叠。

公开(公告)号：US08304906B2

公开(公告)日：2012-11-06

申请号：US12789634

申请日：2010-05-28

Applicant: Cheng-Lin Huang ,  Jiing-Feng Yang ,  Chii-Ping Chen ,  Dian-Hau Chen ,  Yuh-Jier Mii

Inventor： Cheng-Lin Huang ,  Jiing-Feng Yang ,  Chii-Ping Chen ,  Dian-Hau Chen ,  Yuh-Jier Mii

IPC: H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76829 ,  H01L21/76849 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Partial air gap formation for providing interconnect isolation in integrated circuits is described. One embodiment is an integrated circuit (“IC”) structure includes a substrate having two adjacent interconnect features formed thereon; caps formed over and aligned with each of the interconnect features; sidewalls formed on opposing sides of each of the interconnect features and a gap formed between the interconnect features; and a dielectric material layer disposed over the substrate to cover the caps and the gap.

Abstract translation: 描述了用于在集成电路中提供互连隔离的部分气隙形成。 一个实施例是集成电路（IC）结构，其包括其上形成有两个相邻互连特征的基板; 帽形成在每个互连特征上并与其对齐; 形成在每个互连特征的相对侧上的侧壁和在互连特征之间形成的间隙; 以及设置在所述基板上以覆盖所述盖和所述间隙的电介质材料层。

公开(公告)号：US20110198757A1

公开(公告)日：2011-08-18

申请号：US12707969

申请日：2010-02-18

Applicant: Shu-Hui SU ,  Cheng-Lin Huang ,  Jiing-Feng Yang ,  Zhen-Cheng Wu ,  Ren-Guei Wu ,  Dian-Hau Chen ,  Yuh-Jier Mll

Inventor： Shu-Hui SU ,  Cheng-Lin Huang ,  Jiing-Feng Yang ,  Zhen-Cheng Wu ,  Ren-Guei Wu ,  Dian-Hau Chen ,  Yuh-Jier Mll

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  G03F1/00

CPC classification number: H01L23/5226 ,  H01L21/02203 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: A semiconductor structure includes a first metal-containing layer, a dielectric capping layer, a second metal-containing layer, and a conductive pad. The first metal-containing layer includes a set of metal structures, a dielectric filler disposed to occupy a portion of the first metal-containing layer, and an air-gap region defined by at least the set of metal structures and the dielectric filler and abutting at least a portion of the set of metal structures. The second metal-containing layer includes at least a via plug electrically connected to a portion of the set of metal structures. The conductive pad and the via plug do not overlap the air-gap region.

Abstract translation: 半导体结构包括第一含金属层，电介质覆盖层，第二含金属层和导电焊盘。 第一含金属层包括一组金属结构，设置成占据第一含金属层的一部分的介电填料，以及由至少一组金属结构和介电填料界定的气隙区， 该组金属结构的至少一部分。 第二含金属层至少包括与该组金属结构的一部分电连接的通孔塞。 导电焊盘和通孔插头不与气隙区域重叠。

公开(公告)号：US07704886B2

公开(公告)日：2010-04-27

申请号：US12031280

申请日：2008-02-14

Applicant: Li-Lin Su ,  Shing-Chyang Pan ,  Cheng-Lin Huang ,  Ching-Hua Hsieh

Inventor： Li-Lin Su ,  Shing-Chyang Pan ,  Cheng-Lin Huang ,  Ching-Hua Hsieh

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/76843 ,  H01L21/2855 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76873

Abstract: A method of forming an integrated circuit structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a first deposition step to form a seed layer in a first chamber; and performing a first etch step to remove a portion of the seed layer. The method may further include performing a second deposition step to increase the thickness of the seed layer. At least one of the first etch step and the second deposition step is performed in a second chamber different from the first chamber.

Abstract translation: 形成集成电路结构的方法包括形成电介质层; 在介电层中形成开口; 执行第一沉积步骤以在第一室中形成种子层; 以及执行第一蚀刻步骤以去除种子层的一部分。 该方法还可以包括执行第二沉积步骤以增加种子层的厚度。 在与第一室不同的第二室中执行第一蚀刻步骤和第二沉积步骤中的至少一个。

公开(公告)号：US07700479B2

公开(公告)日：2010-04-20

申请号：US11593286

申请日：2006-11-06

Applicant: Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

Inventor： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

IPC: H01L21/4763

CPC classification number: H01L21/02063 ,  H01L21/76807 ,  H01L21/76814

Abstract: A method for fabricating an integrated circuit includes providing a substrate, forming a low-k dielectric layer over the substrate, etching the low-k dielectric layer to form an opening in the low-k dielectric layer wherein an underlying metal is exposed through the opening, performing a remote plasma treatment to the substrate wherein a plasma used for the remote plasma treatment is generated from a plasma generator separated from a chamber in which the substrate is located, forming a diffusion barrier layer in the opening, and filling the opening with a conductive material. The method preferably includes an in-situ plasma treatment in a same chamber as the step of etching the low-k dielectric layer.

Abstract translation: 一种用于制造集成电路的方法包括提供衬底，在衬底上形成低k电介质层，蚀刻低k电介质层以在低k电介质层中形成开口，其中下面的金属通过开口暴露 对基板执行远程等离子体处理，其中用于远程等离子体处理的等离子体从与其中所述基板所在的室分离的等离子体发生器产生，在该开口中形成扩散阻挡层，并且在该开口中填充该开口 导电材料。 该方法优选包括在与蚀刻低k电介质层的步骤相同的室中的原位等离子体处理。

公开(公告)号：US07612451B2

公开(公告)日：2009-11-03

申请号：US11486893

申请日：2006-07-13

Applicant: Chih-Chao Shih ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

Inventor： Chih-Chao Shih ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/53238 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76855 ,  H01L21/76856 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, and a damascene structure in the opening. The damascene structure includes a metallic barrier layer in the opening and in physical contact with the dielectric layer, a conductive material filling the remaining part of the opening, and an interlayer between and adjoining the metallic barrier layer and the conductive material. The interlayer is preferably a metal compound layer.

Abstract translation: 提供了具有改进的电阻率的集成电路结构及其形成方法。 集成电路结构包括电介质层，电介质层中的开口和开口中的镶嵌结构。 镶嵌结构包括开口中的金属阻挡层和与电介质层物理接触的金属阻挡层，填充开口的剩余部分的导电材料以及金属阻挡层和导电材料之间的中间层。 中间层优选为金属化合物层。

公开(公告)号：US20090209106A1

公开(公告)日：2009-08-20

申请号：US12031108

申请日：2008-02-14

Applicant: Li-Lin Su ,  Cheng-Lin Huang ,  Shing-Chyang Pan ,  Ching-Hua Hsieh

Inventor： Li-Lin Su ,  Cheng-Lin Huang ,  Shing-Chyang Pan ,  Ching-Hua Hsieh

IPC: H01L21/311

CPC classification number: H01L21/76843 ,  H01L21/2855 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76873

Abstract: A method of forming a seed layer of an interconnect structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a first deposition step to form the seed layer; and in-situ performing a first etch step to remove a portion of the seed layer. The method may further includes additional deposition and etch steps for forming the seed layer.

Abstract translation: 形成互连结构的籽晶层的方法包括形成介电层; 在介电层中形成开口; 执行第一沉积步骤以形成种子层; 并且原位执行第一蚀刻步骤以去除种子层的一部分。 该方法还可以包括用于形成种子层的附加沉积和蚀刻步骤。

公开(公告)号：US20080012133A1

公开(公告)日：2008-01-17

申请号：US11486893

申请日：2006-07-13

Applicant: Chih-Chao Shih ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

Inventor： Chih-Chao Shih ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

IPC: H01L23/52

CPC classification number: H01L23/53238 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76855 ,  H01L21/76856 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, and a damascene structure in the opening. The damascene structure includes a metallic barrier layer in the opening and in physical contact with the dielectric layer, a conductive material filling the remaining part of the opening, and an interlayer between and adjoining the metallic barrier layer and the conductive material. The interlayer is preferably a metal compound layer.

Abstract translation: 提供了具有改进的电阻率的集成电路结构及其形成方法。 集成电路结构包括电介质层，电介质层中的开口和开口中的镶嵌结构。 镶嵌结构包括开口中的金属阻挡层和与电介质层物理接触的金属阻挡层，填充开口的剩余部分的导电材料以及金属阻挡层和导电材料之间的中间层。 中间层优选为金属化合物层。

公开(公告)号：US20070257369A1

公开(公告)日：2007-11-08

申请号：US11429879

申请日：2006-05-08

Applicant: Cheng-Lin Huang

Inventor： Cheng-Lin Huang

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L21/76834 ,  H01L21/76831

Abstract: An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, an oxide-based barrier layer directly on sidewalls of the opening, and conductive materials filling the remaining portion of the opening.

Abstract translation: 提供了具有改进的电阻率的集成电路结构及其形成方法。 集成电路结构包括电介质层，电介质层中的开口，直接位于开口侧壁上的基于氧化物的阻挡层，以及填充开口的剩余部分的导电材料。