利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

145 条记录 (耗时 0.029 秒)

    Metal bridging monitor for etch and CMP endpoint detection
    61.
    发明授权
    Metal bridging monitor for etch and CMP endpoint detection 失效
    用于蚀刻和CMP端点检测的金属桥接监视器

    公开(公告)号：US07011762B1

    公开(公告)日：2006-03-14

    申请号：US10419534

    申请日：2003-04-21

    申请人： Christopher F. Lyons ,  Ramkumar Subramanian ,  Steven C. Avanzino

    发明人： Christopher F. Lyons ,  Ramkumar Subramanian ,  Steven C. Avanzino

    IPC分类号： C23F1/00 ,  G01R31/00

    CPC分类号： H01L21/3212 ,  H01L21/32051 ,  H01L21/32136 ,  H01L22/26 ,  H01L2924/0002 ,  H01L2924/00

    摘要： One aspect of the present invention relates to a wafer containing a semiconductor substrate, at least one metal layer formed over the semiconductor substrate, and at least one electrical sensor embedded at least one of on and in the wafer to facilitate real time monitoring of the metal layer as it progresses through a subtractive metallization process. Another aspect of the present relates to a system and method for monitoring a subtractive metallization process in real time in order to effectuate an immediate response in the on-going process. The system contains a wafer comprising at least one metal layer formed on a semiconductor substrate, at least one electrical sensor in contact with the wafer and operable to detect and transmit electrical activity associated with the wafer, and an electrical measurement station operable to process electrical activity detected and received from the electrical sensor for monitoring a subtractive metallization process in real-time.

    摘要翻译： 本发明的一个方面涉及包含半导体衬底的晶片，在半导体衬底上形成的至少一个金属层和至少一个嵌入在晶片内和晶片中的至少一个的电传感器，以便于金属的实时监测 当它通过减色金属化过程进行时。 本发明的另一方面涉及一种用于实时监测减色金属化过程以便在持续过程中实现立即响应的系统和方法。 该系统包含晶片，该晶片包括形成在半导体衬底上的至少一个金属层，与晶片接触的至少一个电传感器，其可操作以检测和传输与晶片相关的电活动;以及电测量站，可操作以处理电活动 从电传感器检测和接收，用于实时监测减色金属化处理。

    Ion implantation to modulate amorphous carbon stress
    62.
    发明授权
    Ion implantation to modulate amorphous carbon stress 失效
    离子注入调节无定形碳应力

    公开(公告)号：US06989332B1

    公开(公告)日：2006-01-24

    申请号：US10217730

    申请日：2002-08-13

    申请人： Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Christopher F. Lyons

    发明人： Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Christopher F. Lyons

    IPC分类号： H01L21/302

    CPC分类号： H01L21/32139 ,  C23C16/26 ,  C23C16/56 ,  H01L21/0332

    摘要： A method of manufacturing an integrated circuit includes providing a layer of polysilicon material above a semiconductor substrate. A layer of amorphous carbon is provided above the layer of polysilicon material and inert ions are implanted into the amorphous carbon layer. The layer of amorphous carbon is patterned to form an amorphous carbon mask, and a feature is formed in the layer of polysilicon according to the amorphous carbon mask.

    摘要翻译： 一种制造集成电路的方法包括在半导体衬底之上提供多晶硅材料层。 在多晶硅材料层上方提供无定形碳层，惰性离子注入到无定形碳层中。 将非晶碳层图案化以形成无定形碳掩模，并且根据无定形碳掩模在多晶硅层中形成特征。

    Selective stress-inducing implant and resulting pattern distortion in amorphous carbon patterning
    65.
    发明授权
    Selective stress-inducing implant and resulting pattern distortion in amorphous carbon patterning 失效
    选择性应力诱导植入物和无定形碳图案化导致的图案变形

    公开(公告)号：US06825114B1

    公开(公告)日：2004-11-30

    申请号：US10424675

    申请日：2003-04-28

    申请人： Philip A. Fisher ,  Christopher F. Lyons ,  Srikanteswara Dakshina-Murthy

    发明人： Philip A. Fisher ,  Christopher F. Lyons ,  Srikanteswara Dakshina-Murthy

    IPC分类号： H01L2144

    CPC分类号： H01L21/0332 ,  H01L21/32139 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming a fuse for use in an integrated circuit using an amorphous carbon mask includes providing a mask material layer comprising amorphous carbon over a conductive layer. The mask material layer is doped with nitrogen, and an anti-reflective coating (ARC) feature is formed over the mask layer. A portion of the mask material layer is removed according to the ARC feature to form a mask, and the ARC feature is removed to form a warped mask. The conductive layer is patterned according to the warped mask, the warped mask is removed, and a silicide layer is provided over the patterned conductive layer.

    摘要翻译： 使用非晶碳掩模形成用于集成电路的熔丝的方法包括在导电层上提供包含无定形碳的掩模材料层。 掩模材料层掺杂有氮，并且在掩模层上形成抗反射涂层（ARC）特征。 根据ARC特征去除掩模材料层的一部分以形成掩模，并且去除ARC特征以形成翘曲的掩模。 根据翘曲的掩模对导电层进行图案化，去除翘曲的掩模，并且在图案化的导电层上提供硅化物层。

    Process for forming a photoresist mask
    67.
    发明授权
    Process for forming a photoresist mask 有权
    光刻胶掩模形成工艺

    公开(公告)号：US06689541B1

    公开(公告)日：2004-02-10

    申请号：US09884182

    申请日：2001-06-19

    申请人： Scott A. Bell ,  Todd P. Lukanc ,  Christopher F. Lyons ,  Marina V. Plat ,  Ramkumar Subramanian

    发明人： Scott A. Bell ,  Todd P. Lukanc ,  Christopher F. Lyons ,  Marina V. Plat ,  Ramkumar Subramanian

    IPC分类号： G03C500

    CPC分类号： G03F7/38 ,  G03F7/265 ,  G03F7/40

    摘要： In a process for forming a photoresist mask, a photoresist layer is applied to a substrate. A silyated layer is formed in the photoresist layer. The features of the silyated area correspond to the features of a photoresist mask to be formed. The photoresist layer is then etched to form a photoresist base beneath the silyated area. The photoresist base is etched to remove material from its sides such that it becomes narrower than the silyated area. The silyated area is then removed, leaving a photoresist mask on the substrate.

    摘要翻译： 在形成光致抗蚀剂掩模的工艺中，将光致抗蚀剂层施加到基底上。 在光致抗蚀剂层中形成硅化层。 硅酸盐化区域的特征对应于要形成的光致抗蚀剂掩模的特征。 然后蚀刻光致抗蚀剂层以在硅化区域下方形成光致抗蚀剂基底。 蚀刻光致抗蚀剂基底以从其侧面去除材料，使得它比斯里芬特区域变窄。 然后除去硅酸盐化区域，在基材上留下光刻胶掩模。

    Carbonization process for an etch mask
    69.
    发明授权
    Carbonization process for an etch mask 失效
    刻蚀掩模的碳化工艺

    公开(公告)号：US06627360B1

    公开(公告)日：2003-09-30

    申请号：US09900985

    申请日：2001-07-09

    申请人： Scott A. Bell ,  Christopher F. Lyons

    发明人： Scott A. Bell ,  Christopher F. Lyons

    IPC分类号： G03F900

    CPC分类号： H01L21/32139 ,  G03F7/40 ,  G03F7/405 ,  H01L21/0274 ,  H01L21/28123 ,  H01L21/31155

    摘要： A method of forming an etch mask includes patterning a top surface of a photoresist layer, carbonizing the patterned top surface of the photoresist layer and selectively removing portions of the photoresist layer. Portions of the photoresist layer under the carbonized areas remain. A substrate or a layer above substrate can be etched or processed in accordance with the mask formed from the photoresist layer.

    摘要翻译： 形成蚀刻掩模的方法包括图案化光致抗蚀剂层的顶表面，碳化光致抗蚀剂层的图案化顶表面并选择性地去除光致抗蚀剂层的部分。 在碳化区域下方的光致抗蚀剂层的部分保留。 可以根据由光致抗蚀剂层形成的掩模来蚀刻或处理衬底或衬底上的层。

    Dual bake for BARC fill without voids
    70.
    发明授权
    Dual bake for BARC fill without voids 失效
    双烘烤BARC填充无空隙

    公开(公告)号：US06605546B1

    公开(公告)日：2003-08-12

    申请号：US09901699

    申请日：2001-07-11

    申请人： Ramkumar Subramanian ,  Wolfram Grundke ,  Bhanwar Singh ,  Christopher F. Lyons ,  Marina V. Plat

    发明人： Ramkumar Subramanian ,  Wolfram Grundke ,  Bhanwar Singh ,  Christopher F. Lyons ,  Marina V. Plat

    IPC分类号： H01L21302

    CPC分类号： H01L21/76808

    摘要： A method for forming a semiconductor device comprises forming a first layer over a semiconductor substrate. At least one hole is formed through the first layer. A bottom anti-reflective coating (BARC) layer is formed in the at least one hole. A first heating is performed to heat the BARC layer to a flow temperature. A second heating is performed to heat the BARC layer to a hardening temperature so that the BARC layer hardens, wherein the hardening temperature is greater than the flow temperature. An etch is performed to form a trench in the first layer and over the at least one hole, wherein the hardened BARC layer in the at least one hole acts as an etch resistant layer during the etch. As an alternative to the second heating step, the BARC may be simply hardened. The first and second heating may be performed within a heating chamber without removing the semiconductor substrate.

    摘要翻译： 一种用于形成半导体器件的方法包括在半导体衬底上形成第一层。 通过第一层形成至少一个孔。 在至少一个孔中形成底部抗反射涂层（BARC）层。 执行第一次加热以将BARC层加热至流动温度。 执行第二次加热以将BARC层加热至硬化温度，使得BARC层硬化，其中硬化温度大于流动温度。 进行蚀刻以在第一层中和在至少一个孔上形成沟槽，其中至少一个孔中的硬化的BARC层在蚀刻期间用作耐蚀刻层。 作为第二加热步骤的替代方案，BARC可以简单地硬化。 第一和第二加热可以在加热室内进行，而不去除半导体衬底。