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    Process for etching an organic dielectric using a silyated photoresist mask
    2.
    发明授权
    Process for etching an organic dielectric using a silyated photoresist mask 有权
    使用硅化光致抗蚀剂掩模蚀刻有机电介质的方法

    公开(公告)号：US06660645B1

    公开(公告)日：2003-12-09

    申请号：US10051725

    申请日：2002-01-17

    申请人： Scott A. Bell ,  Todd P. Lukanc ,  Christopher F. Lyons ,  Marina V. Plat ,  Ramkumar Subramanian

    发明人： Scott A. Bell ,  Todd P. Lukanc ,  Christopher F. Lyons ,  Marina V. Plat ,  Ramkumar Subramanian

    IPC分类号： H07L21302

    CPC分类号： H01L21/31144

    摘要： A process for forming a semiconductor device may comprise forming an organic dielectric layer on a substrate, forming a protective layer on the organic dielectric layer, forming a photoresist mask on the protective layer, and silyating the photoresist mask. The protective layer is etched using the silyated photoresist mask as an etch mask, and then the organic dielectric layer is etched using the silyated photoresist mask as an etch mask. Metal may be deposited in a void etched in the organic dielectric layer to form a wiring, contact or via.

    摘要翻译： 用于形成半导体器件的工艺可以包括在衬底上形成有机电介质层，在有机介电层上形成保护层，在保护层上形成光致抗蚀剂掩模，并使光刻胶掩模进行硅化。 使用硅化光致抗蚀剂掩模作为蚀刻掩模蚀刻保护层，然后使用硅化光致抗蚀剂掩模作为蚀刻掩模蚀刻有机介电层。 金属可以沉积在蚀刻在有机介电层中的空隙中以形成布线，接触或通孔。

    Thin resist with nitride hard mask for gate etch application
    3.
    发明授权
    Thin resist with nitride hard mask for gate etch application 有权
    具有栅极蚀刻应用的氮化物硬掩模的薄抗蚀剂

    公开(公告)号：US06309926B1

    公开(公告)日：2001-10-30

    申请号：US09205211

    申请日：1998-12-04

    申请人： Scott A. Bell ,  Christopher F. Lyons ,  Harry J. Levinson ,  Khanh B. Nguyen ,  Fei Wang ,  Chih Yuh Yang

    发明人： Scott A. Bell ,  Christopher F. Lyons ,  Harry J. Levinson ,  Khanh B. Nguyen ,  Fei Wang ,  Chih Yuh Yang

    IPC分类号： H01L218242

    CPC分类号： H01L27/11521 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/32139 ,  H01L27/115

    摘要： A method of forming a gate structure is provided. In the method, a nitride layer is formed on a gate material layer. An ultra-thin photoresist layer is formed on the nitride layer. The ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for the gate. The ultra-thin photoresist layer is used as a mask during a first etch step to transfer the gate pattern to the nitride layer. The first etch step includes an etch chemistry that is selective to the nitride layer over the ultra-thin photoresist layer. The nitride layer is used as a hard mask during a second etch step to form the gate by transferring the gate pattern to the gate material layer via the second etch step.

    摘要翻译： 提供一种形成栅极结构的方法。 在该方法中，在栅极材料层上形成氮化物层。 在氮化物层上形成超薄的光致抗蚀剂层。 用短波长辐射对超薄光致抗蚀剂层进行构图，以限定栅极的图案。 在第一蚀刻步骤期间，将超薄光致抗蚀剂层用作掩模，以将栅极图案转移到氮化物层。 第一蚀刻步骤包括对超薄光致抗蚀剂层上的氮化物层有选择性的蚀刻化学品。 在第二蚀刻步骤期间，氮化物层用作硬掩模，以通过经由第二蚀刻步骤将栅极图案转移到栅极材料层来形成栅极。

    Thin resist with amorphous silicon hard mask for via etch application
    4.
    发明授权
    Thin resist with amorphous silicon hard mask for via etch application 有权
    具有非晶硅硬掩模的薄抗蚀剂，用于通孔蚀刻应用

    公开(公告)号：US06165695A

    公开(公告)日：2000-12-26

    申请号：US203150

    申请日：1998-12-01

    申请人： Chih Yuh Yang ,  Christopher F. Lyons ,  Harry J. Levinson ,  Khanh B. Nguyen ,  Fei Wang ,  Scott A. Bell

    发明人： Chih Yuh Yang ,  Christopher F. Lyons ,  Harry J. Levinson ,  Khanh B. Nguyen ,  Fei Wang ,  Scott A. Bell

    IPC分类号： H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  G03C5/00

    CPC分类号： H01L21/31144 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/76816 ,  Y10S430/168

    摘要： A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and an amorphous silicon layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the amorphous silicon layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the amorphous silicon layer. The first etch step includes an etch chemistry that is selective to the amorphous silicon layer over the ultra-thin photoresist layer and the dielectric layer. The amorphous silicon layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.

    摘要翻译： 提供一种形成通孔结构的方法。 在该方法中，在覆盖第一金属层的抗反射涂层（ARC）层上形成电介质层; 并且在该电介质层上形成非晶硅层。 在非晶硅层上形成超薄光致抗蚀剂层，并用短波长辐射对超薄光致抗蚀剂层进行构图，以限定通孔的图案。 在第一蚀刻步骤期间，将图案化超薄光致抗蚀剂层用作掩模，以将通孔图案转印到非晶硅层。 第一蚀刻步骤包括对超薄光致抗蚀剂层和介电层上的非晶硅层有选择性的蚀刻化学品。 在第二蚀刻步骤期间，非晶硅层用作硬掩模，以通过蚀刻介电层的部分形成对应于通孔图案的接触孔。

    System and method using in situ scatterometry to detect photoresist pattern integrity during the photolithography process
    5.
    发明授权
    System and method using in situ scatterometry to detect photoresist pattern integrity during the photolithography process 有权
    使用原位散射法在光刻过程中检测光致抗蚀剂图案完整性的系统和方法

    公开(公告)号：US07052921B1

    公开(公告)日：2006-05-30

    申请号：US10934192

    申请日：2004-09-03

    申请人： Marina V. Plat ,  Bhanwar Singh ,  Calvin T. Gabriel ,  Christopher F. Lyons ,  Scott A. Bell ,  Ramkumar Subramanian ,  Srikanteswara Dakshina-Murthy

    发明人： Marina V. Plat ,  Bhanwar Singh ,  Calvin T. Gabriel ,  Christopher F. Lyons ,  Scott A. Bell ,  Ramkumar Subramanian ,  Srikanteswara Dakshina-Murthy

    IPC分类号： H01L21/66

    CPC分类号： G03F7/70625 ,  G03F7/70608 ,  H01L22/12

    摘要： The present invention uses in situ scatterometry to determine if a defect (e.g., photoresist erosion, photoresist bending and pattern collapse) is present on a wafer. In one embodiment, in situ scatterometry is used to detect a pattern integrity defect associated with the layer of photoresist. In situ scatterometry produces diffraction data associated with the thickness of the photoresist patterned mask. This data is compared to a model of diffraction data associated with a suitable photoresist thickness. If the measured diffraction data is within an acceptable range, the next step of the photolithography process is carried out. However, if the measured thickness is outside of the suitable range, a defect is detected, and the wafer may be sent for re-working or re-patterned prior to main etch, thereby preventing unnecessary wafer scrap. Another aspect of the present invention allows for a feedback control mechanism to alter a physical parameter of the photolithographic process based upon the in situ scatterometry measurements.

    摘要翻译： 本发明使用原位散射法来确定晶片上是否存在缺陷（例如，光致抗蚀剂侵蚀，光致抗蚀剂弯曲和图案崩溃）。 在一个实施例中，原位散射法用于检测与光致抗蚀剂层相关联的图案完整性缺陷。 原位散射法产生与光致抗蚀剂图案掩模的厚度相关的衍射数据。 将该数据与与合适的光致抗蚀剂厚度相关联的衍射数据的模型进行比较。 如果测量的衍射数据在可接受的范围内，则进行光刻工艺的下一步骤。 然而，如果测量的厚度在合适的范围之外，则检测到缺陷，并且可以在主蚀刻之前将晶片发送用于再加工或重新图案化，从而防止不必要的晶片废料。 本发明的另一方面允许反馈控制机制基于原位散射测量来改变光刻工艺的物理参数。

    Method of strengthening photoresist to prevent pattern collapse
    8.
    发明授权
    Method of strengthening photoresist to prevent pattern collapse 有权
    加强光致抗蚀剂以防止图案塌陷的方法

    公开(公告)号：US06635409B1

    公开(公告)日：2003-10-21

    申请号：US09902568

    申请日：2001-07-12

    申请人： Christopher F. Lyons ,  Scott A. Bell ,  Todd Lukanc ,  Marina V. Plat

    发明人： Christopher F. Lyons ,  Scott A. Bell ,  Todd Lukanc ,  Marina V. Plat

    IPC分类号： G03F700

    CPC分类号： G03F7/40 ,  G03F7/2024

    摘要： There is provided a method for forming a photoresist layer for photolithographic applications which has increased structural strength. The photoresist layer is exposed through a mask and developed. The photoresist layer is then treated to change its material properties before the photoresist layer is dried. Also provided are a semiconductor fabrication method employing a treated photoresist and a composition for a treatable photoresist.

    摘要翻译： 提供了一种形成光刻应用的光致抗蚀剂层的方法，其具有增加的结构强度。 光致抗蚀剂层通过掩模曝光并显影。 然后在光致抗蚀剂层干燥之前，处理光致抗蚀剂层以改变其材料性质。 还提供了使用经处理的光致抗蚀剂和用于可处理光致抗蚀剂的组合物的半导体制造方法。

    Bi-layer trim etch process to form integrated circuit gate structures
    9.
    发明授权
    Bi-layer trim etch process to form integrated circuit gate structures 有权
    双层微调蚀刻工艺形成集成电路门结构

    公开(公告)号：US06541360B1

    公开(公告)日：2003-04-01

    申请号：US09845649

    申请日：2001-04-30

    申请人： Marina V. Plat ,  Scott A. Bell ,  Christopher F. Lyons ,  Ramkumar Subramanian ,  Bhanwar Singh

    发明人： Marina V. Plat ,  Scott A. Bell ,  Christopher F. Lyons ,  Ramkumar Subramanian ,  Bhanwar Singh

    IPC分类号： H01L213205

    CPC分类号： H01L21/0338 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/32139 ,  Y10S438/947 ,  Y10S438/952

    摘要： A bi-layer trim etch process to form integrated circuit gate structures can include depositing an organic underlayer over a layer of polysilicon, depositing an imaging layer over the organic underlayer, patterning the imaging layer, selectively trim etching the organic underlayer to form a pattern, and removing portions of the polysilicon layer using the pattern formed from the removed portions of organic underlayer. Thus, the use of thin imaging layer, that has high etch selectivity to the organic underlayer, allows the use of trim etch techniques without a risk of resist erosion or the aspect ratio pattern collapse. That, in turn, allows for the formation of the gate pattern with widths less than the widths of the pattern of the imaging layer.

    摘要翻译： 用于形成集成电路栅极结构的双层修剪蚀刻工艺可以包括在多晶硅层上沉积有机底层，在有机底层上沉积成像层，图案化成像层，选择性地修整蚀刻有机底层以形成图案， 以及使用由有机底层的去除部分形成的图案去除多晶硅层的部分。 因此，对有机底层具有高蚀刻选择性的薄成像层的使用允许使用微调蚀刻技术，而不会有抗蚀剂侵蚀或长宽比图案崩溃的风险。 这又反过来允许形成具有小于成像层的图案的宽度的宽度的栅极图案。

    RELACS process to double the frequency or pitch of small feature formation
    10.
    发明授权
    RELACS process to double the frequency or pitch of small feature formation 失效
    RELACS过程将小特征形成的频率或间距加倍

    公开(公告)号：US06383952B1

    公开(公告)日：2002-05-07

    申请号：US09794632

    申请日：2001-02-28

    申请人： Ramkumar Subramanian ,  Bhanwar Singh ,  Marina V. Plat ,  Christopher F. Lyons ,  Scott A. Bell

    发明人： Ramkumar Subramanian ,  Bhanwar Singh ,  Marina V. Plat ,  Christopher F. Lyons ,  Scott A. Bell

    IPC分类号： H01L2131

    CPC分类号： H01L21/0271 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338

    摘要： A method of doubling the frequency of small pattern formation. The method includes forming a photoresist layer, and then patterning it. A RELACS polymer is spread over the patterned photoresist layer. Portions of the RELACS polymer on top portions of each patterned photoresist region are removed, by either etching or by polishing them off. Portions between each patterned photoresist region are also removed in this step. The patterned photoresist regions are removed, preferably by a flood exposure and then application of a developer to the exposed photoresist regions. The remaining RELACS polymer regions, which were disposed against respective sidewalls of the patterned photoresist regions, prior to their removal, are then used for forming small pattern regions to be used in a semiconductor device to be formed on the substrate. These small pattern regions can be used to form separate poly-gates.

    摘要翻译： 一种将图案形成加倍的方法。 该方法包括形成光致抗蚀剂层，然后对其进行图案化。 RELACS聚合物分散在图案化的光致抗蚀剂层上。 通过蚀刻或通过抛光，去除每个图案化的光致抗蚀剂区域的顶部上的部分RELACS聚合物。 在该步骤中也去除了每个图案化的光致抗蚀剂区域之间的部分。 去除图案化的光致抗蚀剂区域，优选通过暴露曝光，然后将显影剂施加到曝光的光致抗蚀剂区域。 然后将其去除之前设置在图案化光致抗蚀剂区域的相应侧壁上的剩余RELACS聚合物区域用于形成待用于形成在衬底上的半导体器件中的小图案区域。 这些小图案区域可用于形成单独的多门。