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    METHOD OF FABRICATING PHOTO SENSOR
    61.
    发明申请
    METHOD OF FABRICATING PHOTO SENSOR 有权
    制作照片传感器的方法

    公开(公告)号：US20110165727A1

    公开(公告)日：2011-07-07

    申请号：US13045512

    申请日：2011-03-10

    申请人： Chien-Sen Weng ,  Chih-Wei Chao ,  Chrong-Jung Lin ,  Ya-Chin King

    发明人： Chien-Sen Weng ,  Chih-Wei Chao ,  Chrong-Jung Lin ,  Ya-Chin King

    IPC分类号： H01L31/18

    CPC分类号： H01L31/153 ,  G02F2201/58

    摘要： A method of fabricating a photo sensor includes the following steps. First, a substrate is provided, having a conductive layer, a buffer dielectric layer, a patterned semiconductor layer, a dielectric layer, and a planarization layer disposed thereon from bottom to top, wherein the patterned semiconductor layer comprises a first doped region, an intrinsic region, and a second doped region disposed in order. Then, the planarization layer is patterned to form an opening in the planarization layer to expose a portion of the dielectric layer, wherein the opening is positioned on the intrinsic region and portions of the first and the second doped regions. Thereafter, at least a patterned transparent conductive layer is formed in the opening, covering the boundary of the intrinsic region and the first doped region and the boundary of the intrinsic region and the second doped region.

    摘要翻译： 一种制造光传感器的方法包括以下步骤。 首先，提供具有导电层，缓冲电介质层，图案化半导体层，电介质层和从底部到顶部设置在其上的平坦化层的衬底，其中所述图案化半导体层包括第一掺杂区域， 区域，以及依次布置的第二掺杂区域。 然后，对平坦化层进行图案化以在平坦化层中形成开口，以暴露电介质层的一部分，其中开口位于本征区域和第一和第二掺杂区域的部分上。 此后，至少在开口中形成图案化的透明导电层，覆盖本征区域和第一掺杂区域以及本征区域和第二掺杂区域的边界的边界。

    High aspect ratio shallow trench using silicon implanted oxide
    64.
    发明授权
    High aspect ratio shallow trench using silicon implanted oxide 有权
    使用硅注入氧化物的高纵横比浅沟槽

    公开(公告)号：US06576558B1

    公开(公告)日：2003-06-10

    申请号：US10262999

    申请日：2002-10-02

    申请人： Chrong-Jung Lin ,  Hsin-Ming Chen

    发明人： Chrong-Jung Lin ,  Hsin-Ming Chen

    IPC分类号： H01L21302

    CPC分类号： H01L21/76237 ,  H01L21/76235

    摘要： A trench is etched through the layers of pad oxide and silicon nitride that have been deposited on a substrate, the patterned layer of photoresist is left in place. A tilt angle nitrogen implant is performed into the surface of the substrate, a deep shallow STI trench is etched into the surface of the substrate. An oxygen implant of moderate intensity is performed in the created STI trench, the photoresist is removed. An anneal is performed on the implanted oxygen. A liner oxide is grown within the opening, High Density Plasma (HDP) oxide is deposited inside the opening and the top surface of the remaining silicon oxide. CMP is performed to the surface of the HDP oxide down to the surface of the pad oxide that completes the formation of the STI region under the first embodiment of the invention. The invention can be further extended by creating a LOCOS layer at the bottom of the STI opening or by further etching the bottom of the STI opening. Both extensions are to be implemented prior to growing the oxide liner.

    摘要翻译： 通过已经沉积在衬底上的衬垫氧化物和氮化硅层蚀刻沟槽，将图案化的光致抗蚀剂层留在原位。 在衬底的表面中进行倾斜角氮注入，深浅的STI沟槽被蚀刻到衬底的表面中。 在产生的STI沟槽中进行中等强度的氧注入，去除光致抗蚀剂。 对植入的氧进行退火。 在开口内生长衬里氧化物，将高密度等离子体（HDP）氧化物沉积在剩余氧化硅的开口和顶表面内。 在本发明的第一实施例中，对HDP氧化物的表面进行CMP直到氧化垫表面，完成STI区的形成。 通过在STI开口的底部产生LOCOS层或通过进一步蚀刻STI开口的底部，可进一步扩展本发明。 两个扩展部分都将在生长氧化物衬垫之前实现。

    NON-VOLATILE MEMORY WITH RESISTIVE ELEMENT AND MANUFACTURING METHOD THEREOF
    65.
    发明申请
    NON-VOLATILE MEMORY WITH RESISTIVE ELEMENT AND MANUFACTURING METHOD THEREOF 有权
    具有电阻元件的非易失性存储器及其制造方法

    公开(公告)号：US20150325626A1

    公开(公告)日：2015-11-12

    申请号：US14504563

    申请日：2014-10-02

    申请人： Chrong-Jung Lin

    发明人： Chrong-Jung Lin

    IPC分类号： H01L27/24 ,  H01L45/00

    CPC分类号： H01L27/2436 ,  H01L29/66795 ,  H01L29/785 ,  H01L45/04 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16

    摘要： A non-volatile memory includes a substrate, a fin structure, a gate structure, a transition layer, and a metal layer. The fin structure is protruded from the substrate. A first source/drain region and a second source/drain region are formed in the fin structure. The gate structure covers a top surface and two lateral surfaces of a part of the fin structure. The gate structure is arranged between the first source/drain region and the second source/drain region. The transition layer is in contact with the second source/drain region. The metal layer is in contact with the transition layer. By setting or resetting the transition layer, a resistance value of the transition layer is correspondingly changed.

    摘要翻译： 非易失性存储器包括衬底，鳍结构，栅极结构，过渡层和金属层。 翅片结构从基板突出。 第一源极/漏极区域和第二源极/漏极区域形成在鳍状结构中。 栅极结构覆盖鳍结构的一部分的顶表面和两个侧表面。 栅极结构布置在第一源极/漏极区域和第二源极/漏极区域之间。 过渡层与第二源/漏区接触。 金属层与过渡层接触。 通过设置或重置过渡层，相应地改变过渡层的电阻值。

    Non-volatile semiconductor device, and method of operating the same
    66.
    发明授权
    Non-volatile semiconductor device, and method of operating the same 有权
    非易失性半导体器件及其操作方法

    公开(公告)号：US08837227B2

    公开(公告)日：2014-09-16

    申请号：US13438660

    申请日：2012-04-03

    申请人： Chrong-Jung Lin ,  Ya-Chin King

    发明人： Chrong-Jung Lin ,  Ya-Chin King

    IPC分类号： G11C16/04 ,  H01L29/788

    CPC分类号： G11C16/0408 ,  H01L29/7883

    摘要： A non-volatile semiconductor device and a method for operating the same are disclosed, where the non-volatile semiconductor device includes a gate dielectric layer, a p-type floating gate, a coupling gate, a first p-type source/drain, a second p-type source/drain, a first contact plug and a second contact plug. The gate dielectric layer is formed on a n-type semiconductor substrate. The p-type floating gate is formed on the gate dielectric layer. The first p-type source/drain and the second p-type source/drain are formed in the n-type semiconductor substrate. The first and second contact plugs are formed on the first and second p-type source/drains respectively. The coupling gate consists essentially of a capacitor dielectric layer and a third contact plug, where the capacitor dielectric layer is formed on the p-type floating gate, and the third contact plug is formed on the capacitor dielectric layer.

    摘要翻译： 公开了一种非易失性半导体器件及其操作方法，其中非易失性半导体器件包括栅极介电层，p型浮置栅极，耦合栅极，第一p型源极/漏极， 第二p型源极/漏极，第一接触插塞和第二接触插塞。 栅介质层形成在n型半导体衬底上。 p型浮栅形成在栅介质层上。 第一p型源极/漏极和第二p型源极/漏极形成在n型半导体衬底中。 第一和第二接触塞分别形成在第一和第二p型源极/漏极上。 耦合栅极基本上由电容器介质层和第三接触插塞构成，其中电容器电介质层形成在p型浮置栅极上，第三接触插塞形成在电容器介电层上。

    Non-volatile semiconductor device, and method of operating the same
    67.
    发明授权
    Non-volatile semiconductor device, and method of operating the same 有权
    非易失性半导体器件及其操作方法

    公开(公告)号：US08724398B2

    公开(公告)日：2014-05-13

    申请号：US13438642

    申请日：2012-04-03

    申请人： Chrong-Jung Lin ,  Ya-Chin King

    发明人： Chrong-Jung Lin ,  Ya-Chin King

    IPC分类号： G11C16/04 ,  G11C16/16

    CPC分类号： G11C16/16 ,  G11C16/0416 ,  H01L27/11521

    摘要： A non-volatile semiconductor device and a method for operating the same are disclosed, where the non-volatile semiconductor device includes a gate dielectric layer, a n-type floating gate, a coupling gate, a first n-type source/drain, a second n-type source/drain, a first contact plug and a second contact plug. The gate dielectric layer is formed on a p-type semiconductor substrate. The n-type floating gate is formed on the gate dielectric layer. The first n-type source/drain and the second n-type source/drain are formed in the p-type semiconductor substrate. The first and second contact plugs are formed on the first and second n-type source/drains respectively. The coupling gate consists essentially of a capacitor dielectric layer and a third contact plug, where the capacitor dielectric layer is formed on the n-type floating gate, and the third contact plug is formed on the capacitor dielectric layer.

    摘要翻译： 公开了一种非易失性半导体器件及其操作方法，其中非易失性半导体器件包括栅极电介质层，n型浮动栅极，耦合栅极，第一n型源极/漏极， 第二n型源极/漏极，第一接触插塞和第二接触插塞。 栅电介质层形成在p型半导体衬底上。 n型浮栅形成在栅介质层上。 第一n型源极/漏极和第二n型源极/漏极形成在p型半导体衬底中。 第一和第二接触塞分别形成在第一和第二n型源极/漏极上。 耦合栅极基本上由电容器介电层和第三接触插塞构成，其中电容器电介质层形成在n型浮置栅极上，第三接触插塞形成在电容器介电层上。

    Tunable current driver and operating method thereof
    69.
    发明授权
    Tunable current driver and operating method thereof 有权
    可调电流驱动器及其操作方法

    公开(公告)号：US08184486B2

    公开(公告)日：2012-05-22

    申请号：US12344268

    申请日：2008-12-25

    申请人： Chrong-Jung Lin ,  Ya-Chin King

    发明人： Chrong-Jung Lin ,  Ya-Chin King

    IPC分类号： G11C16/06

    CPC分类号： G09G3/3233 ,  G09G2300/0847 ,  G09G2320/0295 ,  G09G2320/043

    摘要： A tunable current driver comprising a semiconductor memory device and a selective transistor is provided, in which one of the source/drain pair of the semiconductor memory device is electrically coupled with a lighting device, and one of the source/drain pair of the selective transistor is electrically coupled with the gate electrode of the semiconductor memory device. The semiconductor memory device not only acts as “drive transistor” to drive the lighting device, but also is capable of adjusting the threshold voltage thereof.

    摘要翻译： 提供了一种包括半导体存储器件和选择性晶体管的可调电流驱动器，其中半导体存储器件的源极/漏极对中的一个与照明器件电耦合，并且选择晶体管的源极/漏极对之一 与半导体存储器件的栅电极电耦合。 半导体存储器件不仅用作“驱动晶体管”来驱动照明器件，而且还能够调节其阈值电压。

    ONE-TIME PROGRAMMABLE READ-ONLY MEMORY
    70.
    发明申请
    ONE-TIME PROGRAMMABLE READ-ONLY MEMORY 审中-公开
    一次性可编程只读存储器

    公开(公告)号：US20100006924A1

    公开(公告)日：2010-01-14

    申请号：US12171301

    申请日：2008-07-11

    申请人： Hsin-Ming Chen ,  Shao-Chang Huang ,  Shih-Chen Wang ,  Tsung-Mu Lai ,  Ming-Chou Ho ,  Chrong-Jung Lin

    发明人： Hsin-Ming Chen ,  Shao-Chang Huang ,  Shih-Chen Wang ,  Tsung-Mu Lai ,  Ming-Chou Ho ,  Chrong-Jung Lin

    IPC分类号： H01L27/112

    CPC分类号： H01L27/112 ,  H01L27/11206 ,  H01L27/11521

    摘要： A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a third doped region, a first dielectric layer, a select gate, a second dielectric layer, a first channel, a second channel and a silicide layer is provided. The first doped region, the second doped region and the third doped region are disposed apart in a substrate. The first dielectric layer is disposed on the substrate between the first doped region and the second doped region. The select gate is disposed on the first dielectric layer. The second dielectric layer is disposed on the substrate between the second doped region and the third doped region. The silicide layer is disposed on the first doped region, the second doped region and the third doped region. The OTP-ROM stores data by a punch-through effect occurring between the second doped region and the third doped region.

    摘要翻译： 一种包括衬底，第一掺杂区域，第二掺杂区域，第三掺杂区域，第一介电层，选择栅极，第二介电层，第一沟道 ，提供第二通道和硅化物层。 第一掺杂区域，第二掺杂区域和第三掺杂区域设置在衬底中。 第一介电层设置在第一掺杂区和第二掺杂区之间的衬底上。 选择栅极设置在第一电介质层上。 第二介电层设置在第二掺杂区和第三掺杂区之间的衬底上。 硅化物层设置在第一掺杂区域，第二掺杂区域和第三掺杂区域上。 OTP-ROM通过发生在第二掺杂区域和第三掺杂区域之间的穿透效应来存储数据。