公开(公告)号：US08089798B2

公开(公告)日：2012-01-03

申请号：US12627244

申请日：2009-11-30

申请人： Tsung-Mu Lai ,  Shao-Chang Huang ,  Wen-hao Ching ,  Chun-Hung Lu ,  Shih-Chen Wang ,  Ming-Chou Ho

发明人： Tsung-Mu Lai ,  Shao-Chang Huang ,  Wen-hao Ching ,  Chun-Hung Lu ,  Shih-Chen Wang ,  Ming-Chou Ho

IPC分类号： G11C17/00

CPC分类号： H01L27/112 ,  G11C17/16 ,  G11C17/18 ,  H01L27/11206

摘要： A method for operating a one-time programmable read-only memory (OTP-ROM) is provided. The OTP-ROM comprises a first gate and a second gate respectively disposed on a gate dielectric layer between a first doped region and a second doped region on a substrate, wherein the first gate is adjacent to the first doped region and coupled to the first doped region, the second gate is adjacent to the second doped region, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. The method comprises a step of programming the OTP-ROM under the conditions that a voltage of the second doped region is higher than a voltage of the first doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the first doped region and the substrate are at a reference voltage.

摘要翻译： 提供了一种用于操作一次性可编程只读存储器（OTP-ROM）的方法。 OTP-ROM包括分别设置在衬底上的第一掺杂区域和第二掺杂区域之间的栅极电介质层上的第一栅极和第二栅极，其中第一栅极与第一掺杂区域相邻并耦合到第一掺杂区域 所述第二栅极与所述第二掺杂区相邻，所述第一栅极电耦合接地，并且通过击穿效应对所述OTP-ROM进行编程。 该方法包括在第二掺杂区域的电压高于第一掺杂区域的电压的条件下对OTP-ROM进行编程的步骤，第二栅极的电压高于阈值电压以通过 第二掺杂区域和第一掺杂区域和衬底处于参考电压。

公开(公告)号：US20100073985A1

公开(公告)日：2010-03-25

申请号：US12627244

申请日：2009-11-30

申请人： Tsung-Mu Lai ,  Shao-Chang Huang ,  Wen-hao Ching ,  Chun-Hung Lu ,  Shih-Chen Wang ,  Ming-Chou Ho

发明人： Tsung-Mu Lai ,  Shao-Chang Huang ,  Wen-hao Ching ,  Chun-Hung Lu ,  Shih-Chen Wang ,  Ming-Chou Ho

IPC分类号： G11C17/08

CPC分类号： H01L27/112 ,  G11C17/16 ,  G11C17/18 ,  H01L27/11206

摘要： A method for operating a one-time programmable read-only memory (OTP-ROM) is provided. The OTP-ROM comprises a first gate and a second gate respectively disposed on a gate dielectric layer between a first doped region and a second doped region on a substrate, wherein the first gate is adjacent to the first doped region and coupled to the first doped region, the second gate is adjacent to the second doped region, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. The method comprises a step of programming the OTP-ROM under the conditions that a voltage of the second doped region is higher than a voltage of the first doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the first doped region and the substrate are at a reference voltage.

摘要翻译： 提供了一种用于操作一次性可编程只读存储器（OTP-ROM）的方法。 OTP-ROM包括分别设置在衬底上的第一掺杂区域和第二掺杂区域之间的栅极电介质层上的第一栅极和第二栅极，其中第一栅极与第一掺杂区域相邻并耦合到第一掺杂区域 所述第二栅极与所述第二掺杂区相邻，所述第一栅极电耦合接地，并且通过击穿效应对所述OTP-ROM进行编程。 该方法包括在第二掺杂区域的电压高于第一掺杂区域的电压的条件下对OTP-ROM进行编程的步骤，第二栅极的电压高于阈值电压以通过 第二掺杂区域和第一掺杂区域和衬底处于参考电压。

公开(公告)号：US20100002344A1

公开(公告)日：2010-01-07

申请号：US12166342

申请日：2008-07-02

申请人： Shao-Chang Huang ,  Wei-Yao Lin ,  Tsung-Mu Lai

发明人： Shao-Chang Huang ,  Wei-Yao Lin ,  Tsung-Mu Lai

IPC分类号： H02H9/00

CPC分类号： G11C7/1078 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1084 ,  G11C29/1201

摘要： A high voltage tolerance circuit includes a first transistor, a second transistor, a third transistor, and a latch-up device. The first transistor and the second transistor are controlled by a control signal. The gate of the third transistor is coupled to a ground through the first transistor. The gate of the third transistor is coupled to an I/O pad through the second transistor. The third transistor is coupled between a power supply and a node. The latch-up device is coupled between the node and the I/O pad.

摘要翻译： 高电压容限电路包括第一晶体管，第二晶体管，第三晶体管和闭锁装置。 第一晶体管和第二晶体管由控制信号控制。 第三晶体管的栅极通过第一晶体管耦合到地。 第三晶体管的栅极通过第二晶体管耦合到I / O焊盘。 第三晶体管耦合在电源和节点之间。 闩锁装置耦合在节点和I / O焊盘之间。

公开(公告)号：US20080296701A1

公开(公告)日：2008-12-04

申请号：US11956633

申请日：2007-12-14

申请人： Tsung-Mu Lai ,  Shao-Chang Huang ,  Wen-hao Ching ,  Chun-Hung Lu ,  Shih-Chen Wang ,  Ming-Chou Ho

发明人： Tsung-Mu Lai ,  Shao-Chang Huang ,  Wen-hao Ching ,  Chun-Hung Lu ,  Shih-Chen Wang ,  Ming-Chou Ho

IPC分类号： H01L27/112

CPC分类号： H01L27/112 ,  G11C17/16 ,  G11C17/18 ,  H01L27/11206

摘要： A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a gate dielectric layer, a first gate and a second gate. The substrate is of a first conductive type. The first doped region and the second doped region are of a second conductive type and are separately disposed in the substrate. The gate dielectric layer is disposed on the substrate between the first doped region and the second doped region. The first gate and the second gate are disposed on the gate dielectric layer, respectively. The first gate is adjacent to the first doped region, while the second gate is adjacent to the second doped region. Here, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect.

摘要翻译： 一种包括衬底，第一掺杂区域，第二掺杂区域，栅极电介质层，第一栅极和第二栅极的可编程只读存储器（OTP-ROM）。 衬底是第一导电类型。 第一掺杂区域和第二掺杂区域是第二导电类型，并且分别设置在衬底中。 栅电介质层设置在第一掺杂区和第二掺杂区之间的衬底上。 第一栅极和第二栅极分别设置在栅极介电层上。 第一栅极与第一掺杂区相邻，而第二栅极与第二掺杂区相邻。 这里，第一个栅极电耦合接地，OTP-ROM通过击穿效应进行编程。

公开(公告)号：US20070145366A1

公开(公告)日：2007-06-28

申请号：US11684241

申请日：2007-03-09

申请人： Hua-Shu Wu ,  Tsung-Mu Lai ,  Ming-Chih Chang ,  Che-Rong Laing

发明人： Hua-Shu Wu ,  Tsung-Mu Lai ,  Ming-Chih Chang ,  Che-Rong Laing

IPC分类号： H01L23/58

CPC分类号： B81C1/00896

摘要： A method and a structure are provided for preventing lift-off of a semiconductor monitor pattern from a substrate . A semiconductor structure and a semiconductor monitor structure are formed on a substrate. A material layer is formed covering the semiconductor monitor structure. A part of the semiconductor structure is removed without removing the semiconductor monitor structure, by using the material layer as an etch protection layer. A mask for the method is also provided. The mask includes a clear area and a dark area. The dark area prevents a semiconductor monitor structure from being subjected to exposure so as to form a material layer covering the semiconductor monitor structure and prevent removal of the semiconductor monitor structure from the substrate while a part of a semiconductor structure is removed.

摘要翻译： 提供了一种用于防止半导体监视器图案从基板剥离的方法和结构。 半导体结构和半导体监视器结构形成在基板上。 形成覆盖半导体监视器结构的材料层。 通过使用材料层作为蚀刻保护层，半导体结构的一部分被去除而不去除半导体监视器结构。 还提供了该方法的掩码。 面具包括清晰的区域和暗区。 暗区防止半导体监视器结构受到曝光，从而形成覆盖半导体监视器结构的材料层，并且在半导体结构的一部分被去除的同时防止从衬底移除半导体监视器结构。

公开(公告)号：US20060189023A1

公开(公告)日：2006-08-24

申请号：US11064985

申请日：2005-02-23

申请人： Fa-Yuan Chang ,  Hua-Shu Wu ,  Tsung-Mu Lai ,  Chau-Yang Wu

发明人： Fa-Yuan Chang ,  Hua-Shu Wu ,  Tsung-Mu Lai ,  Chau-Yang Wu

IPC分类号： H01L21/46

CPC分类号： B81C1/00047

摘要： A method of making a MEMS device including providing a first substrate with an insulator layer thereon. A holder is attached to the insulator layer, and the first substrate is thinned. Thereafter, cavities are formed in the first substrate and the first substrate is flipped over and bonded to an integrated circuit wafer with the cavities facing the integrated circuit wafer. The holder is removed to provide a first substrate with cavities formed therein facing the integrated circuit wafer and an insulator layer overlying the first substrate.

摘要翻译： 一种制造MEMS器件的方法，包括在其上提供具有绝缘体层的第一衬底。 保持器附接到绝缘体层，并且第一基板变薄。 此后，在第一基板中形成空腔，并将第一基板翻转并结合到集成电路晶片，其中空腔面向集成电路晶片。 保持器被移除以提供第一基板，其中形成有面向集成电路晶片的空腔和覆盖第一基板的绝缘体层。

公开(公告)号：US07965481B2

公开(公告)日：2011-06-21

申请号：US12166342

申请日：2008-07-02

申请人： Shao-Chang Huang ,  Wei-Yao Lin ,  Tsung-Mu Lai

发明人： Shao-Chang Huang ,  Wei-Yao Lin ,  Tsung-Mu Lai

IPC分类号： H02H9/00

CPC分类号： G11C7/1078 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1084 ,  G11C29/1201

摘要： A high voltage tolerance circuit includes a first transistor, a second transistor, a third transistor, and a latch-up device. The first transistor and the second transistor are controlled by a control signal. The gate of the third transistor is coupled to a ground through the first transistor. The gate of the third transistor is coupled to an I/O pad through the second transistor. The third transistor is coupled between a power supply and a node. The latch-up device is coupled between the node and the I/O pad.

摘要翻译： 高电压容限电路包括第一晶体管，第二晶体管，第三晶体管和闭锁装置。 第一晶体管和第二晶体管由控制信号控制。 第三晶体管的栅极通过第一晶体管耦合到地。 第三晶体管的栅极通过第二晶体管耦合到I / O焊盘。 第三晶体管耦合在电源和节点之间。 闩锁装置耦合在节点和I / O焊盘之间。

公开(公告)号：US20090065908A1

公开(公告)日：2009-03-12

申请号：US12254493

申请日：2008-10-20

申请人： Chia-Hua Chang ,  Huaa-Shu Wu ,  Tsung-Mu Lai

发明人： Chia-Hua Chang ,  Huaa-Shu Wu ,  Tsung-Mu Lai

IPC分类号： H01L23/58 ,  H01L23/28

CPC分类号： B81C1/00142

摘要： Methods of fabricating a microelectromechanical structure are provided. An exemplary embodiment of a method of fabricating a microelectromechanical structure comprises providing a substrate. A first patterned sacrificial layer is formed on portions of the substrate, the first patterned sacrificial layer comprises a bulk portion and a protrusion portion. A second patterned sacrificial layer is formed over the first sacrificial layer, covering the protrusion portion and portions of the bulk portion of the first patterned sacrificial layer, wherein the second patterned sacrificial layer does not cover sidewalls of the first patterned sacrificial layer. An element layer is formed over the substrate, covering portions of the substrate, the first patterned sacrificial layer and second patterned sacrificial layer. The first and second patterned sacrificial layers are removed, leaving a microstructure on the substrate.

摘要翻译： 提供了制造微机电结构的方法。 制造微机电结构的方法的示例性实施例包括提供基底。 第一图案化牺牲层形成在衬底的部分上，第一图案化牺牲层包括主体部分和突出部分。 第二图案化牺牲层形成在第一牺牲层上，覆盖突出部分和第一图案化牺牲层的主体部分的部分，其中第二图案化牺牲层不覆盖第一图案化牺牲层的侧壁。 元件层形成在衬底上，覆盖衬底的部分，第一图案化牺牲层和第二图案化牺牲层。 去除第一和第二图案化牺牲层，在基底上留下微结构。

公开(公告)号：US07468327B2

公开(公告)日：2008-12-23

申请号：US11451424

申请日：2006-06-13

申请人： Chia-Hua Chang ,  Hua-Shu Wu ,  Tsung-Mu Lai

发明人： Chia-Hua Chang ,  Hua-Shu Wu ,  Tsung-Mu Lai

IPC分类号： H01L21/31

CPC分类号： B81C1/00142

摘要： Methods of fabricating a microelectromechanical structure are provided. An exemplary embodiment of a method of fabricating a microelectromechanical structure comprises providing a substrate. A first patterned sacrificial layer is formed on portions of the substrate, the first patterned sacrificial layer comprises a bulk portion and a protrusion portion. A second patterned sacrificial layer is formed over the first sacrificial layer, covering the protrusion portion and portions of the bulk portion of the first patterned sacrificial layer, wherein the second patterned sacrificial layer does not cover sidewalls of the first patterned sacrificial layer. An element layer is formed over the substrate, covering portions of the substrate, the first patterned sacrificial layer and second patterned sacrificial layer. The first and second patterned sacrificial layers are removed, leaving a microstructure on the substrate.

摘要翻译： 提供了制造微机电结构的方法。 制造微机电结构的方法的示例性实施例包括提供基底。 第一图案化牺牲层形成在衬底的部分上，第一图案化牺牲层包括主体部分和突出部分。 第二图案化牺牲层形成在第一牺牲层上，覆盖突出部分和第一图案化牺牲层的主体部分的部分，其中第二图案化牺牲层不覆盖第一图案化牺牲层的侧壁。 元件层形成在衬底上，覆盖衬底的部分，第一图案化牺牲层和第二图案化牺牲层。 去除第一和第二图案化牺牲层，在基底上留下微结构。

公开(公告)号：US07295374B2

公开(公告)日：2007-11-13

申请号：US11066668

申请日：2005-02-25

申请人： Ming-Chih Chang ,  Hua-Shu Wu ,  Tsung-Mu Lai

发明人： Ming-Chih Chang ,  Hua-Shu Wu ,  Tsung-Mu Lai

IPC分类号： G02B27/10 ,  B29D11/00 ,  G03C5/00

CPC分类号： B29D11/00365 ,  G02B3/00 ,  Y10S359/90

摘要： A method of manufacturing a micro-lens is disclosed. The method includes providing a convex photoresist surface, forming a lens mold on the convex photoresist surface, removing the lens mold from the convex photoresist surface, forming a micro-lens in the lens mold and removing the micro-lens from the lens mold.

摘要翻译： 公开了一种制造微透镜的方法。 该方法包括提供凸起的光致抗蚀剂表面，在凸形光致抗蚀剂表面上形成透镜模具，从凸起光致抗蚀剂表面移除透镜模具，在透镜模具中形成微透镜并从透镜模具中移除微透镜。