中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

69 records (took 0.026 seconds)

    SYSTEMS AND METHODS FOR CREATING FREQUENCY-DEPENDENT NETLIST
    61.
    发明申请
    SYSTEMS AND METHODS FOR CREATING FREQUENCY-DEPENDENT NETLIST 有权
    用于创建频率依赖的网络列表的系统和方法

    公开(公告)号：US20130014070A1

    公开(公告)日：2013-01-10

    申请号：US13176823

    申请日：2011-07-06

    Applicant: Ke-Ying SU ,  Ching-Shun Yang ,  Jui-Feng Kuan ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Huang-Yu Chen ,  Chung-Hsing Wang

    Inventor： Ke-Ying SU ,  Ching-Shun Yang ,  Jui-Feng Kuan ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Huang-Yu Chen ,  Chung-Hsing Wang

    IPC: G06F17/50

    CPC classification number: G06F17/5036 ,  G06F17/5077 ,  G06F17/5081

    Abstract: A method includes creating a technology file including data for an integrated circuit including at least one die coupled to an interposer and a routing between the at least one die and the interposer, b) creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the at least one die and in the interposer based on the technology file, c) simulating a performance of the integrated circuit based on the netlist, d) adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and e) repeating steps c) and d) to optimize the at least one of the capacitive or inductive couplings.

    Abstract translation: 一种方法包括创建包括用于集成电路的数据的技术文件，所述集成电路包括耦合到插入器的至少一个管芯以及所述至少一个管芯和所述插入器之间的布线，b）创建包括接近电容或电感 基于所述技术文件，在所述至少一个管芯中和所述插入器中的导体之间的耦合，c）基于所述网表来模拟所述集成电路的性能，d）基于所述网表调整所述至少一个管芯和所述插入器之间的布线 模拟以减少电容或电感耦合中的至少一个，以及e）重复步骤c）和d）以优化电容或电感耦合中的至少一个。

    Systematic method for variable layout shrink
    62.
    发明授权
    Systematic method for variable layout shrink 有权
    变量布局收缩的系统方法

    公开(公告)号：US08286119B2

    公开(公告)日：2012-10-09

    申请号：US12617046

    申请日：2009-11-12

    Applicant: Fu-Chieh Hsu ,  Louis Chao-Chiuan Liu ,  Lee-Chung Lu ,  Yi-Kan Cheng

    Inventor： Fu-Chieh Hsu ,  Louis Chao-Chiuan Liu ,  Lee-Chung Lu ,  Yi-Kan Cheng

    IPC: G06F17/50

    CPC classification number: G06F17/5068

    Abstract: A method for integrated circuit design includes providing a layout of an integrated circuit; determining key parameters of the integrated circuit; determining target values of the key parameters; and performing a first shrinkage of the layout using a first shrink percentage to generate a shrunk layout. The shrunk layout is evaluated by generating values of the key parameters from the shrunk layout. A portion of the values of the key parameters failing to meet respective ones of the target values is found. Guidelines for tuning manufacturing processes of the shrunk layout are provided, so that the portion of the values of the key parameters can meet the respective ones of the target values.

    Abstract translation: 一种用于集成电路设计的方法包括提供集成电路的布局; 确定集成电路的关键参数; 确定关键参数的目标值; 并且使用第一收缩百分比来执行布局的第一收缩以产生收缩的布局。 通过从缩小布局生成关键参数的值来评估收缩布局。 找到关键参数的值的一部分不能满足相应的目标值。 提供用于调整缩小布局的制造过程的指南，使得关键参数的值的部分可以满足相应的目标值。

    Double patterning friendly lithography method and system
    63.
    发明授权
    Double patterning friendly lithography method and system 有权
    双重图案友好光刻方法和系统

    公开(公告)号：US08245174B2

    公开(公告)日：2012-08-14

    申请号：US12549087

    申请日：2009-08-27

    Applicant: Yi-Kan Cheng ,  Ru-Gun Liu ,  Lee-Chung Lu

    Inventor： Yi-Kan Cheng ,  Ru-Gun Liu ,  Lee-Chung Lu

    IPC: G06F17/50

    CPC classification number: G06F17/5068

    Abstract: A method includes receiving an identification of a plurality of cells to be included in an integrated circuit (IC) layout, including a list of pairs of cells within the plurality of cells to be connected to each other. First routing paths are identified, to connect a maximum number of the pairs of cells using one-dimensional (1-D) routing between cells within those pairs of cells. Second routing paths are selected from a predetermined set of two-dimensional (2-D) routing patterns to connect any of the pairs of cells which cannot be connected by 1-D routing. The first and second routing paths are output to a machine readable storage medium to be read by a control system for controlling a semiconductor fabrication process to fabricate the IC.

    Abstract translation: 一种方法包括接收要包括在集成电路（IC）布局中的多个单元的标识，包括要彼此连接的多个单元格内的单元对对的列表。 识别出第一路由路径，以便在这些小区对内的小区之间使用一维（1-D）路由连接最大数量的小区对。 从预定的二维（2-D）路由模式集合中选择第二路由路径，以连接不能通过1-D路由连接的任何一对小区。 第一和第二路由路径被输出到机器可读存储介质，以由用于控制制造IC的半导体制造工艺的控制系统读取。

    DOUBLE PATTERNING FRIENDLY LITHOGRAPHY METHOD AND SYSTEM
    66.
    发明申请
    DOUBLE PATTERNING FRIENDLY LITHOGRAPHY METHOD AND SYSTEM 有权
    双重图案友好的方法和系统

    公开(公告)号：US20110023002A1

    公开(公告)日：2011-01-27

    申请号：US12549087

    申请日：2009-08-27

    Applicant: Yi-Kan Cheng ,  Ru-Gun Liu ,  Lee-Chung Lu

    Inventor： Yi-Kan Cheng ,  Ru-Gun Liu ,  Lee-Chung Lu

    IPC: G06F17/50

    CPC classification number: G06F17/5068

    Abstract: A method includes receiving an identification of a plurality of cells to be included in an integrated circuit (IC) layout, including a list of pairs of cells within the plurality of cells to be connected to each other. First routing paths are identified, to connect a maximum number of the pairs of cells using one-dimensional (1-D) routing between cells within those pairs of cells. Second routing paths are selected from a predetermined set of two-dimensional (2-D) routing patterns to connect any of the pairs of cells which cannot be connected by 1-D routing. The first and second routing paths are output to a machine readable storage medium to be read by a control system for controlling a semiconductor fabrication process to fabricate the IC.

    Abstract translation: 一种方法包括接收要包括在集成电路（IC）布局中的多个单元的标识，包括要彼此连接的多个单元格内的单元对对的列表。 识别出第一路由路径，以便在这些小区对内的小区之间使用一维（1-D）路由连接最大数量的小区对。 从预定的二维（2-D）路由模式集合中选择第二路由路径，以连接不能通过1-D路由连接的任何一对小区。 第一和第二路由路径被输出到机器可读存储介质，以由用于控制制造IC的半导体制造工艺的控制系统读取。

    Method for smart dummy insertion to reduce run time and dummy count
    67.
    发明授权
    Method for smart dummy insertion to reduce run time and dummy count 有权
    用于智能虚拟插入的方法，以减少运行时间和虚拟计数

    公开(公告)号：US07801717B2

    公开(公告)日：2010-09-21

    申请号：US11625658

    申请日：2007-01-22

    Applicant: Gwan Sin Chang ,  Yi-Kan Cheng ,  Cliff Hou

    Inventor： Gwan Sin Chang ,  Yi-Kan Cheng ,  Cliff Hou

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F17/5068 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method involves providing a circuit pattern, generating a density report for the circuit pattern that identifies a feasible area for dummy insertion, simulating a planarization process with the density report and identifying a hot spot on the circuit pattern, inserting a virtual dummy pattern in the feasible area and adjusting the density report accordingly, and thereafter simulating the planarization process with the adjusted density until the hot spot is eliminated.

    Abstract translation: 一种方法包括提供一种电路图案，产生用于识别用于虚拟插入的可行区域的电路图案的密度报告，用密度报告模拟平面化处理，并识别电路图案上的热点，将虚拟虚拟图案插入到 相应地调整密度报告，然后以调整的密度模拟平坦化处理，直到消除热点。

    Advisory System for Verifying Sensitive Circuits in Chip-Design
    68.
    发明申请
    Advisory System for Verifying Sensitive Circuits in Chip-Design 有权
    芯片设计中验证敏感电路的咨询系统

    公开(公告)号：US20090172617A1

    公开(公告)日：2009-07-02

    申请号：US12054195

    申请日：2008-03-24

    Applicant: Chi-Heng Huang ,  Gary Lin ,  Chu-Fu Chen ,  Yi-Kan Cheng ,  Fu-Lung Hsueh

    Inventor： Chi-Heng Huang ,  Gary Lin ,  Chu-Fu Chen ,  Yi-Kan Cheng ,  Fu-Lung Hsueh

    IPC: G06F17/50

    CPC classification number: G06F17/5036 ,  G06F17/5009

    Abstract: A verification system for verifying an integrated circuit design is provided. The verification system includes a functional block finding module configured to identify potential sensitive circuits in the integrated circuit design; and a search module. The search module is configured to find sensitive circuits from the potential sensitive circuits; and verify the sensitive circuits.

    Abstract translation: 提供了用于验证集成电路设计的验证系统。 验证系统包括：功能块查找模块，被配置为识别集成电路设计中的潜在敏感电路; 和搜索模块。 搜索模块被配置为从潜在敏感电路中找到敏感电路; 并验证敏感电路。

    Method For Smart Dummy Insertion To Reduce Run Time And Dummy Count
    69.
    发明申请
    Method For Smart Dummy Insertion To Reduce Run Time And Dummy Count 有权
    用于智能虚拟插入的方法可减少运行时间和虚拟计数

    公开(公告)号：US20080176343A1

    公开(公告)日：2008-07-24

    申请号：US11625658

    申请日：2007-01-22

    Applicant: Gwan Sin Chang ,  Yi-Kan Cheng ,  Cliff Hou

    Inventor： Gwan Sin Chang ,  Yi-Kan Cheng ,  Cliff Hou

    IPC: H01L21/00

    CPC classification number: G06F17/5072 ,  G06F17/5068 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method involves providing a circuit pattern, generating a density report for the circuit pattern that identifies a feasible area for dummy insertion, simulating a planarization process with the density report and identifying a hot spot on the circuit pattern, inserting a virtual dummy pattern in the feasible area and adjusting the density report accordingly, and thereafter simulating the planarization process with the adjusted density until the hot spot is eliminated.

    Abstract translation: 一种方法包括提供一种电路图案，产生用于识别用于虚拟插入的可行区域的电路图案的密度报告，用密度报告模拟平面化处理，并识别电路图案上的热点，将虚拟虚拟图案插入到 相应地调整密度报告，然后以调整的密度模拟平坦化处理，直到消除热点。

Patent Agency Ranking