公开(公告)号：US20200278753A1

公开(公告)日：2020-09-03

申请号：US16875006

申请日：2020-05-15

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Srdjan MARIJANOVIC ,  Drew KINNEY ,  Luke LAPOINTE ,  Siddharth MARU ,  Tejasvi DAS ,  Anthony S. DOY ,  Zhong YOU

IPC: G06F3/01 ,  G06F3/041 ,  G06F3/044 ,  G06F3/045 ,  G01D5/20 ,  G01D5/243

Abstract: A system may include a tactile actuator for providing tactile feedback and a resonant phase sensing system. The resonant phase sensing system may include a resistive-inductive-capacitive sensor and a measurement circuit communicatively coupled to the resistive-inductive-capacitive sensor and the tactile actuator. The resistive-inductive-capacitive sensor may be configured to measure phase information associated with the resistive-inductive-capacitive sensor, based on the phase information, detect an indication of human interaction with the system proximate to the resistive-inductive-capacitive sensor, and trigger the tactile actuator to generate tactile feedback responsive to detecting the indication of human interaction.

公开(公告)号：US20200177167A1

公开(公告)日：2020-06-04

申请号：US16784392

申请日：2020-02-07

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Jing BAI ,  Tejasvi DAS ,  Xin ZHAO ,  Lei ZHU ,  Xiaofan FEI

IPC: H03K3/01 ,  H03K17/687

Abstract: A driver system may include a first n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a first terminal of a supply voltage and configured to drive the output when the first n-type field-effect transistor is activated, a second n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a second terminal of the supply voltage and configured to drive the output when the second n-type field-effect transistor is activated, a high-side capacitor coupled to the output of the driver system, and a low-side capacitor coupled to the second terminal of the supply voltage, wherein the high-side capacitor and the low-side capacitor are configured to track and correct for mismatches between a first resistance of the first n-type field-effect transistor and a second resistance of the second n-type field-effect transistor.

公开(公告)号：US20200036352A1

公开(公告)日：2020-01-30

申请号：US16181762

申请日：2018-11-06

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Lei ZHU ,  Tejasvi DAS ,  John L. MELANSON ,  Wai-shun Wilson SHUM ,  Jing BAI ,  Xin ZHAO ,  Xiaofan FEI

IPC: H03G3/30 ,  H03F3/217 ,  H03F3/187 ,  H03F3/387

Abstract: A system may include a digital modulator configured to modulate an input signal received at an input of the digital modulator to generate a modulated input signal at an output of the digital modulator, a digital gain element having a digital gain and coupled to the digital modulator, an open-loop Class-D amplifier coupled to an output of the digital modulator and configured to amplify the modulated input signal, wherein the open-loop Class-D amplifier is powered from a variable power supply having a variable supply voltage which is variable in response to one or more characteristics of the input signal, and a control circuit configured to control the digital gain to approximately cancel changes in an analog gain of the open-loop Class-D amplifier due to variation in the variable supply voltage in response to the one or more characteristics of the input signal.

公开(公告)号：US20190260377A1

公开(公告)日：2019-08-22

申请号：US16162960

申请日：2018-10-17

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Jing BAI ,  Tejasvi DAS ,  Xin ZHAO ,  Lei ZHU ,  Xiaofan FEI

IPC: H03K17/687 ,  H03K17/06 ,  G06F3/01

Abstract: A driver system may include a first n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a first terminal of a supply voltage and configured to drive the output when the first n-type field-effect transistor is activated, a second n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a second terminal of the supply voltage and configured to drive the output when the second n-type field-effect transistor is activated, a high-side capacitor coupled to the output of the driver system, and a low-side capacitor coupled to the second terminal of the supply voltage, wherein the high-side capacitor and the low-side capacitor are configured to track and correct for mismatches between a first resistance of the first n-type field-effect transistor and a second resistance of the second n-type field-effect transistor.

公开(公告)号：US20190253031A1

公开(公告)日：2019-08-15

申请号：US16140663

申请日：2018-09-25

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Amar VELLANKI ,  Tejasvi DAS ,  John L. MELANSON

IPC: H03G3/30 ,  H03F3/217

CPC classification number: H03G3/3031 ,  H03F3/217

Abstract: A multi-path subsystem may include a first processing path, a second processing path, a mixed signal return path, and a calibration engine configured to: estimate and cancel a direct current (DC) offset of the mixed signal return path, estimate and cancel a DC offset between the first processing path and the second processing path, estimate and cancel a phase difference between the first processing path and a sum of the second processing path and the mixed signal return path, estimate and cancel a return path gain of the mixed signal return path, and track and correct for a gain difference between the first processing path and the second processing path.

公开(公告)号：US20190115886A1

公开(公告)日：2019-04-18

申请号：US16133045

申请日：2018-09-17

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Tejasvi DAS ,  Alan Mark MORTON ,  Xin ZHAO ,  Lei ZHU ,  Xiaofan FEI ,  Johann G. GABORIAU ,  John L. MELANSON ,  Amar VELLANKI

IPC: H03G3/30 ,  H03F3/187 ,  H04R3/00

Abstract: A system may include a digital pulse width modulator subsystem, a first path coupled to an output of the digital pulse width modulator subsystem, a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, a controller to select between the first path and the second path for processing a signal based on one or more characteristics of the signal, wherein a first gain of the first path and a second gain of the second path are approximately equal at the time of switching selection between the first path and the second path or vice versa, in order to minimize artifacts due to the switching.

公开(公告)号：US20170374456A1

公开(公告)日：2017-12-28

申请号：US15195626

申请日：2016-06-28

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Tejasvi DAS ,  Anand ILANGO

IPC: H04R3/00 ,  H03F3/181 ,  H03F3/20

CPC classification number: H04R3/007 ,  H03F1/305 ,  H03F1/34 ,  H03F3/181 ,  H03F3/187 ,  H03F3/20 ,  H03F3/72 ,  H03F2200/03 ,  H03F2200/129 ,  H03F2200/381 ,  H03F2200/408 ,  H03G3/348 ,  H03M1/66

Abstract: A method may be provided for powering up or down a playback path comprising a digital-to-analog converter (DAC) for generating a non-ground-centered analog intermediate voltage centered at a common-mode voltage and coupled to a driver for generating a ground-centered playback path output voltage at an output of the driver wherein the output of the driver is clamped via a finite impedance to a ground voltage. The method may include transitioning continuously or in a plurality of discrete steps the analog intermediate voltage from an initial voltage to the common-mode voltage such that the transitioning is substantially inaudible at the output of the driver. A method for operating an output clamp of an output driver stage of a playback path may include transitioning continuously or in a plurality of discrete steps an impedance of the output clamp in order to match an output offset of the output driver stage in order to minimize audio artifacts appearing at an output of the output driver stage.