公开(公告)号：US08116140B2

公开(公告)日：2012-02-14

申请号：US12757399

申请日：2010-04-09

申请人： Yingda Dong ,  Yupin K. Fong ,  Gerrit Jan Hemink

发明人： Yingda Dong ,  Yupin K. Fong ,  Gerrit Jan Hemink

IPC分类号： G11C16/04

CPC分类号： G11C16/04 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C2211/5621 ,  G11C2211/5622

摘要： In a memory system, a programming waveform reduces program noise by using sets of multiple adjacent sub-pulses which have a saw-tooth shape. In a set, an initial sub-pulse steps up from an initial level such as 0 V to a peak level, then steps down to an intermediate level, which is above the initial level. One or more subsequent sub-pulses of the set can step up from an intermediate level to a peak level, and then step back down to an intermediate level. A last sub-pulse of the set can step up from an intermediate level to a peak level, and then step back down to the initial level. A verify operation is performed after the set of sub-pulses. The number of sub-pulses per set can decrease in successive sets until a solitary pulse is applied toward the end of a programming operation.

摘要翻译： 在存储器系统中，编程波形通过使用具有锯齿形状的多个相邻子脉冲的集合来减少编程噪声。 在一组中，初始子脉冲从初始电平（例如0V）升高到峰值电平，然后降至高于初始电平的中间电平。 该集合的一个或多个后续子脉冲可以从中间电平升高到峰值电平，然后降低到中间电平。 集合的最后一个子脉冲可以从中间电平升高到峰值电平，然后降低到初始电平。 在子脉冲组之后执行验证操作。 每组的子脉冲数可以在连续的集合中减小，直到在编程操作结束时施加孤立脉冲。

公开(公告)号：US20110044102A1

公开(公告)日：2011-02-24

申请号：US12544113

申请日：2009-08-19

申请人： Yingda Dong ,  Tien-chien Kuo ,  Gerrit Jan Hemink

发明人： Yingda Dong ,  Tien-chien Kuo ,  Gerrit Jan Hemink

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/30 ,  G11C16/3418 ,  G11C2211/5641

摘要： Techniques are disclosed herein for programming memory arrays to achieve high program/erase cycle endurance. In some aspects, only selected word lines (WL) are programmed with other WLs remaining unprogrammed. As an example, only the even word lines are programmed with the odd WLs left unprogrammed. After all of the even word lines are programmed and the data block is to be programmed with new data, the block is erased. Later, only the odd word lines are programmed. The data may be transferred to a block that stores multiple bit per memory cell prior to the erase. In one aspect, the data is programmed in a checkerboard pattern with some memory cells programmed and others left unprogrammed. Later, after erasing the data, the previously unprogrammed part of the checkerboard pattern is programmed with remaining cells unprogrammed.

摘要翻译： 本文公开了用于编程存储器阵列以实现高编程/擦除周期耐久性的技术。 在某些方面，只有选择的字线（WL）被编程，其他WL保持未编程。 作为示例，只有偶数字线被编程，剩余的未编程的奇数WL。 在所有偶数字线被编程并且数据块要用新数据编程之后，块被擦除。 之后，只有奇数字线被编程。 数据可以被传送到在擦除之前存储多个存储单元的位的块。 在一个方面，数据以棋盘格式编程，其中编程了一些存储器单元，而其他存储器单元未被编程。 之后，在擦除数据之后，棋盘格图案的以前未编程的部分被编程为剩余的单元未编程。

公开(公告)号：US20100329002A1

公开(公告)日：2010-12-30

申请号：US12490557

申请日：2009-06-24

申请人： Yingda Dong ,  Cynthia Hsu

发明人： Yingda Dong ,  Cynthia Hsu

IPC分类号： G11C16/04

CPC分类号： G11C16/3454 ,  G11C7/04 ,  G11C11/5628 ,  G11C16/3418

摘要： Program disturb is reduced in a non-volatile storage system during a programming operation by determining a susceptibility of a set of storage elements to program disturb and taking a corresponding precautionary measure, if needed, to reduce the likelihood of program disturb occurring. During programming of a lower page of data, a natural threshold voltage distribution of the set of storage elements is determined by tracking storage elements which are programmed to a particular state, and determining how many program pulses are need for a number N1 and a number N2>N1 of the storage elements to reach the particular state. Temperature and word line position can also be used to determine the susceptibility to program disturb. A precautionary measure can involve using a higher pass voltage, or abandoning programming of an upper page of data or an entire block. In some cases, programming continues with no precautionary measure.

摘要翻译： 在编程操作期间，在非易失性存储系统中通过确定一组存储元件对编程干扰的敏感度并在需要时采取相应的预防措施来减少程序干扰发生的可能性，从而减少了程序干扰。 在下一页数据的编程期间，通过对被编程到特定状态的存储元件进行跟踪，并且确定需要数量N1和数N2的多个编程脉冲来确定该组存储元件的自然阈值电压分布 > N1的存储元素达到特定状态。 温度和字线位置也可用于确定编程干扰的敏感度。 预防措施可以涉及使用较高的通过电压，或放弃对数据的上部页面或整个块的编程。 在某些情况下，方案继续采取预防措施。

公开(公告)号：US07796430B2

公开(公告)日：2010-09-14

申请号：US12211348

申请日：2008-09-16

申请人： Jeffrey W. Lutze ,  Yingda Dong

发明人： Jeffrey W. Lutze ,  Yingda Dong

IPC分类号： G11C16/04

CPC分类号： G11C16/3418

摘要： A non-volatile storage system which reduces program disturb. Multiple boosting modes are implemented while programming non-volatile storage. For example, self-boosting, local self-boosting, erased area self-boosting and revised erased area self-boosting may be used. One or more switching criteria are used to determine when to switch to a different boosting mode. The boosting mode may be used to prevent program disturb in unselected NAND strings while storage elements are being programmed in selected NAND strings. By switching boosting modes, an optimal boosting mode can be used as conditions change. The boosting mode can be switched based on various criteria such as program pulse number, program pulse amplitude, program pass number, the position of a selected word line, whether coarse or fine programming is used, whether a storage element reaches a program condition and/or a number of program cycles of the non-volatile storage device.

摘要翻译： 一种减少程序干扰的非易失性存储系统。 在编程非易失性存储时实现多种升压模式。 例如，可以使用自我增强，局部自我增强，消除区域自增强和修改的擦除区域自增强。 使用一个或多个切换标准来确定何时切换到不同的升压模式。 当存储元件被编程在所选择的NAND串中时，升压模式可用于防止未选择的NAND串中的程序干扰。 通过切换升压模式，可以在条件变化时使用最佳升压模式。 可以基于各种标准来切换升压模式，例如程序脉冲数，程序脉冲幅度，程序通过次数，所选字线的位置，是使用粗调还是精细编程，存储元件是否达到程序状态和/ 或非易失性存储设备的多个程序周期。

公开(公告)号：US07623387B2

公开(公告)日：2009-11-24

申请号：US11609813

申请日：2006-12-12

申请人： Yingda Dong ,  Jeffrey W. Lutze

发明人： Yingda Dong ,  Jeffrey W. Lutze

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/3418 ,  G11C16/3427

摘要： Non-volatile storage with reduced program disturb is provided by boosting unselected NAND strings in an array so that a source side channel, on a source side of a selected word line, is boosted before a drain side channel, on a drain side of the selected word line. In one approach, a first boost mode is used when the selected word line is a lower or intermediate word line. In the first boost mode, boosting of the source and drain side channels is initiated concurrently. A second boost mode is used when the selected word line is a higher word line. In the second boost mode, boosting of the source side channel occurs early relative to the boosting of the drain side channel. Either boost mode include an isolation voltage which tends to isolate the source and drain side channels from one another.

摘要翻译： 通过将阵列中未选择的NAND串升压来提供具有减少的编程干扰的非易失性存储器，使得在所选择的字线的源极侧上的源极通道在所选择的漏极侧的漏极侧之前被提升在漏极侧通道之前 字线。 在一种方法中，当所选字线是较低或中间字线时，使用第一升压模式。 在第一升压模式中，同时启动源极和漏极侧通道的升压。 当所选字线是较高字线时，使用第二升压模式。 在第二升压模式中，源极侧沟道的升压相对于漏极侧沟道的升压而早期发生。 升压模式包括易于将源极和漏极侧通道彼此隔离的隔离电压。

公开(公告)号：US07468911B2

公开(公告)日：2008-12-23

申请号：US11555856

申请日：2006-11-02

申请人： Jeffrey W. Lutze ,  Yingda Dong

发明人： Jeffrey W. Lutze ,  Yingda Dong

IPC分类号： G11C16/04

CPC分类号： G11C16/3418

摘要： A non-volatile storage system which reduces program disturb. Multiple boosting modes are implemented while programming non-volatile storage. For example, self-boosting, local self-boosting, erased area self-boosting and revised erased area self-boosting may be used. One or more switching criteria are used to determine when to switch to a different boosting mode. The boosting mode may be used to prevent program disturb in unselected NAND strings while storage elements are being programmed in selected NAND strings. By switching boosting modes, an optimal boosting mode can be used as conditions change. The boosting mode can be switched based on various criteria such as program pulse number, program pulse amplitude, program pass number, the position of a selected word line, whether coarse or fine programming is used, whether a storage element reaches a program condition and/or a number of program cycles of the non-volatile storage device.

摘要翻译： 一种减少程序干扰的非易失性存储系统。 在编程非易失性存储时实现多种升压模式。 例如，可以使用自我增强，局部自我增强，消除区域自增强和修改的擦除区域自增强。 使用一个或多个切换标准来确定何时切换到不同的升压模式。 当存储元件被编程在所选择的NAND串中时，升压模式可用于防止未选择的NAND串中的程序干扰。 通过切换升压模式，可以在条件变化时使用最佳升压模式。 可以基于各种标准来切换升压模式，例如程序脉冲数，程序脉冲幅度，程序通过次数，所选字线的位置，是使用粗调还是精细编程，存储元件是否达到程序状态和/ 或非易失性存储设备的多个程序周期。

公开(公告)号：US07463522B2

公开(公告)日：2008-12-09

申请号：US11745092

申请日：2007-05-07

申请人： Yingda Dong ,  Jeffrey W. Lutze ,  Shih-Chung Lee ,  Gerrit Jan Hemink ,  Ken Oowada

发明人： Yingda Dong ,  Jeffrey W. Lutze ,  Shih-Chung Lee ,  Gerrit Jan Hemink ,  Ken Oowada

IPC分类号： G11C16/00

CPC分类号： G11C8/08 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5621

摘要： Non-volatile storage in which program disturb is reduced by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before the channel is boosted on a drain side of the isolation word line. Further, storage elements near the isolation word line are kept in a conducting state during the source side boosting so that the source side channel is connected to the drain side channel. In this way, in selected NAND strings, source side boosting can not occur and thus program disturb due to source side boosting can be prevented. After the source side boosting, the source side channel is isolated from the drain side channel, and drain side boosting is performed.

摘要翻译： 通过防止所选择的NAND串中的源极升压来减少编程干扰的非易失性存储。 使用包括隔离字线的自增强模式。 禁止的NAND串的通道区域在隔离字线的漏极侧的通道升压之前在隔离字线的源极侧被升压。 此外，在源侧升压期间，隔离字线附近的存储元件保持导通状态，使得源极侧沟道连接到漏极侧沟道。 以这种方式，在选择的NAND串中，不能发生源侧升压，因此可以防止由于源极侧升压而导致的编程干扰。 在源侧升压之后，源侧沟道与漏极侧沟道隔离，并且进行漏极侧升压。

公开(公告)号：US20080278999A1

公开(公告)日：2008-11-13

申请号：US12060487

申请日：2008-04-01

申请人： Yingda Dong ,  Jeffrey W. Lutze

发明人： Yingda Dong ,  Jeffrey W. Lutze

IPC分类号： G11C16/12

CPC分类号： G11C16/3418

摘要： Program disturb is reduced during programming of non-volatile storage by providing a boosting scheme in which isolation voltage are applied to two word lines to create a source side channel region on a source side of one isolation word line, an intermediate channel region between the isolation word lines and a drain side channel region on a drain side of the other isolation word line. Further, during a programming operation, the source and drain side channel regions are boosted early while the intermediate channel region is boosted later, when a program pulse is applied. This approach prevents charge leakage from the intermediate channel region to the source side, avoiding disturb of already programmed storage elements, while also allowing electrons to flow from the intermediate channel region to the drain side channel region, which makes the boosting of the intermediate channel region easier.

摘要翻译： 在非易失性存储器的编程期间通过提供一种升压方案来减少在非易失性存储器编程期间的编程干扰，其中隔离电压施加到两个字线以在一个隔离字线的源极侧产生源极侧沟道区，隔离层之间的中间沟道区 字线和另一个隔离字线的漏极侧的漏极侧沟道区。 此外，在编程操作期间，当施加编程脉冲时，源极和漏极侧通道区域早期被提升，而中间沟道区域稍后升压。 这种方法防止从中间通道区域到源极的电荷泄漏，避免已经编程的存储元件的干扰，同时还允许电子从中间沟道区域流到漏极侧沟道区域，这使得中间沟道区域的升压 更轻松。

公开(公告)号：US20080056001A1

公开(公告)日：2008-03-06

申请号：US11933649

申请日：2007-11-01

申请人： Nima Mokhlesi ,  Yingda Dong

发明人： Nima Mokhlesi ,  Yingda Dong

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： Errors can occur when reading the threshold voltage of a programmed non-volatile storage element due to at least two mechanisms: (1) capacitive coupling between neighboring floating gates and (2) changing conductivity of the channel area after programming (referred to as back pattern effect). To account for coupling between neighboring floating gates, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell. To account for the back pattern effect, a first voltage is used during a verify operation for unselected word lines that have been subjected to a programming operation and a second voltage is used for unselected word lines that have not been subjected to a programming operation. The combination of these two techniques provides for more accurate storage and retrieval of data.

摘要翻译： 由于至少两种机制，读取编程的非易失性存储元件的阈值电压时可能会发生错误：（1）相邻浮动栅极之间的电容耦合和（2）编程后改变通道区域的电导率（称为反向图案 影响）。 为了考虑相邻浮动栅极之间的耦合，对于特定存储器单元的读取处理将为相邻存储器单元提供补偿，以便减少相邻存储器单元对特定存储器单元具有的耦合效应。 为了解决背模式效应，在对已经经过编程操作的未选字线的验证操作期间使用第一电压，并且对未经过编程操作的未选字线使用第二电压。 这两种技术的组合提供了更准确的数据存储和检索。

公开(公告)号：US07310272B1

公开(公告)日：2007-12-18

申请号：US11421884

申请日：2006-06-02

申请人： Nima Mokhlesi ,  Yingda Dong

发明人： Nima Mokhlesi ,  Yingda Dong

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： Errors can occur when reading the threshold voltage of a programmed non-volatile storage element due to at least two mechanisms: (1) capacitive coupling between neighboring floating gates and (2) changing conductivity of the channel area after programming (referred to as back pattern effect). To account for coupling between neighboring floating gates, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell. To account for the back pattern effect, a first voltage is used during a verify operation for unselected word lines that have been subjected to a programming operation and a second voltage is used for unselected word lines that have not been subjected to a programming operation. The combination of these two techniques provides for more accurate storage and retrieval of data.

摘要翻译： 由于至少两种机制，读取编程的非易失性存储元件的阈值电压时可能会发生错误：（1）相邻浮动栅极之间的电容耦合和（2）编程后改变通道区域的电导率（称为反向图案 影响）。 为了考虑相邻浮动栅极之间的耦合，对于特定存储器单元的读取处理将为相邻存储器单元提供补偿，以便减少相邻存储器单元对特定存储器单元具有的耦合效应。 为了解决背模式效应，在对已经经过编程操作的未选字线的验证操作期间使用第一电压，并且对未经过编程操作的未选字线使用第二电压。 这两种技术的组合提供了更准确的数据存储和检索。