公开(公告)号：US20070081406A1

公开(公告)日：2007-04-12

申请号：US11246586

申请日：2005-10-07

申请人： David Boerstler ,  Eskinder Hailu ,  Subramanian Iyer ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Subramanian Iyer ,  Jieming Qi

IPC分类号： G11C17/18

CPC分类号： G11C17/18 ,  G11C17/16

摘要： An apparatus and method for providing a reprogrammable electrically programmable fuse (eFuse) are provided. With the apparatus and method, a pair of eFuses are provided coupled to programming current sources and sensing current sources. When the pair of eFuses is to be programmed, a first programming current is applied to a first eFuse to thereby increase the resistance of the first eFuse by an incremental amount. When the pair of eFuses is to be returned to an unprogrammed state, a second programming current source is applied to a second eFuse to thereby increase a resistance of the second eFuse to be greater than the resistance of the first eFuse. When the sensing current is applied to the eFuses, a difference in the resulting voltages across the eFuses is identified and used to indicate whether the reprogrammable eFuse is in a programmed state or unprogrammed state.

摘要翻译： 提供了一种用于提供可再编程电可编程熔丝（eFuse）的设备和方法。 利用该装置和方法，提供一对耦合到编程电流源并感测电流源的eFuses。 当要对一对eFuse进行编程时，将第一编程电流施加到第一eFuse，从而增加第一eFuse的电阻增量。 当一对eFuse将返回到未编程状态时，第二编程电流源被施加到第二eFuse，从而将第二eFuse的电阻增加到大于第一eFuse的电阻。 当感应电流被施加到eFuse时，识别出eFuses上产生的电压的差异，并用于指示可重新编程的eFuse是否处于编程状态或未编程状态。

公开(公告)号：US20070057697A1

公开(公告)日：2007-03-15

申请号：US11227026

申请日：2005-09-15

申请人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： G01R29/02

CPC分类号： G01R31/31708 ,  G01R31/31725

摘要： An apparatus and method for verifying glitch-free operation of a multiplexer are provided. The apparatus includes a circuit having a plurality of flip-flop elements that receive as inputs the plurality of clock signals that are inputs to the multiplexer, and a corresponding synchronized output signal of a decoder generated based on control inputs to the decoder. The synchronized output signals from the decoder are used as trigger signals to the plurality of flip-flops. The flip-flops sample the clock signals based upon the trigger signals and provide outputs to a logic gate. The logic gate operates on the outputs from the flip-flops to generate an output signal indicative of whether glitch-free operation is verified or is not verified.

公开(公告)号：US07969250B2

公开(公告)日：2011-06-28

申请号：US12129811

申请日：2008-05-30

申请人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi

发明人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi

IPC分类号： H03B27/00

CPC分类号： H03L7/183 ,  H03L7/0998

摘要： A design structure for a programmable interpolative voltage controlled oscillator (VCO) with adjustable frequency range output is provided. Programmable delay cells whose size is modifiable based on control inputs to the programmable delay cells are utilized. A different set of control inputs may be provided to programmable delay cells of an inner sub-ring from the set of control inputs provided to programmable delay cells of a main ring of the VCO. The minimum frequency output of the VCO is governed by the main ring programmable delay cell strength with the maximum frequency output of the VCO being governed by a ratio of strengths of the main ring programmable delay cells to the inner sub-ring programmable delay cell. By modifying the control inputs to the inner sub-ring and main ring programmable delay cells, the minimum and maximum frequency outputs, and thus the range between these two frequency outputs, are made programmable.

摘要翻译： 提供了具有可调频率范围输出的可编程内插压控振荡器（VCO）的设计结构。 利用基于可编程延迟单元的控制输入来修改尺寸的可编程延迟单元。 从提供给VCO的主环的可编程延迟单元的控制输入的集合可以向内部子环的可编程延迟单元提供不同的一组控制输入。 VCO的最小频率输出由主环路可编程延迟单元强度控制，VCO的最大频率输出由主环可编程延迟单元与内部子环可编程延迟单元的强度比控制。 通过修改内部子环和主环可编程延迟单元的控制输入，可以将最小和最大频率输出，从而将这两个频率输出之间的范围编程为可编程。

公开(公告)号：US20090183136A1

公开(公告)日：2009-07-16

申请号：US12129811

申请日：2008-05-30

申请人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi

发明人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi

IPC分类号： G06F17/50

CPC分类号： H03L7/183 ,  H03L7/0998

摘要： A design structure for a programmable interpolative voltage controlled oscillator (VCO) with adjustable frequency range output is provided. Programmable delay cells whose size is modifiable based on control inputs to the programmable delay cells are utilized. A different set of control inputs may be provided to programmable delay cells of an inner sub-ring from the set of control inputs provided to programmable delay cells of a main ring of the VCO. The minimum frequency output of the VCO is governed by the main ring programmable delay cell strength with the maximum frequency output of the VCO being governed by a ratio of strengths of the main ring programmable delay cells to the inner sub-ring programmable delay cell. By modifying the control inputs to the inner sub-ring and main ring programmable delay cells, the minimum and maximum frequency outputs, and thus the range between these two frequency outputs, are made programmable.

摘要翻译： 提供了具有可调频率范围输出的可编程内插压控振荡器（VCO）的设计结构。 利用基于可编程延迟单元的控制输入来修改尺寸的可编程延迟单元。 从提供给VCO的主环的可编程延迟单元的控制输入的集合可以向内部子环的可编程延迟单元提供不同的一组控制输入。 VCO的最小频率输出由主环路可编程延迟单元强度控制，VCO的最大频率输出由主环可编程延迟单元与内部子环可编程延迟单元的强度比控制。 通过修改内部子环和主环可编程延迟单元的控制输入，可以将最小和最大频率输出，从而将这两个频率输出之间的范围编程为可编程。

公开(公告)号：US20080191809A1

公开(公告)日：2008-08-14

申请号：US12098483

申请日：2008-04-07

申请人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi ,  Mike Shen

发明人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi ,  Mike Shen

IPC分类号： H03K3/03

CPC分类号： H03L7/0995 ,  H03K3/0315 ,  H03K5/133

摘要： An interleaved voltage-controlled oscillator (VCO) is disclosed. The VCO includes a ring circuit comprising a series connection of main logic inverter gates, a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates, at least one temperature compensation circuit comprising a logic inverter gate in series connection with one or more field effect transistors, the field effect transistor responsive to a compensating voltage input that is proportional to temperature, and an electronic circuit in signal communication with the at least one temperature compensation circuit and configured to provide a voltage signal responsive to temperature. Each delay element includes a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages, and a proportional section, comprising controls for regulating signal transmission through at least one logic inverter gate.

公开(公告)号：US07358785B2

公开(公告)日：2008-04-15

申请号：US11278842

申请日：2006-04-06

申请人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： H03K3/017

CPC分类号： H03K5/1534 ,  H03K5/156 ,  H03K2005/00293

摘要： An apparatus and method for extracting a maximum pulse width of a pulse width limiter are provided. The apparatus and method of the illustrative embodiments performs such extraction using a circuit that is configured to eliminate the majority of the delay cells utilized in the circuit arrangement described in commonly assigned and co-pending U.S. patent application Ser. No. 11/109,090 (hereafter referred to as the '090 application). The elimination of these delay cells is made possible in one illustrative embodiment by replacing an OR gate in the circuit configuration of the '090 application with an edge triggered re-settable latch. The replacement of the OR gate with the edge triggered re-settable latch reduces the amount of chip area used in addition to the power consumption of the circuit.

摘要翻译： 提供了一种用于提取脉冲宽度限制器的最大脉冲宽度的装置和方法。 说明性实施例的装置和方法使用被配置为消除在共同转让和共同未决的美国专利申请Ser中描述的电路装置中使用的大多数延迟单元的电路来执行这种提取。 第11 / 109,090号（以下简称“090”）。 在一个说明性实施例中，通过用'边缘触发的可重新设定的锁存器'替换'090应用的电路配置中的或门，可以消除这些延迟单元。 利用边沿触发的可重新设置的锁存器替换或门可以减少除了电路功耗之外使用的芯片面积。

公开(公告)号：US20080012617A1

公开(公告)日：2008-01-17

申请号：US11457637

申请日：2006-07-14

申请人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： A Duty Cycle Correction (DCC) circuit is provide in which pairs of field effect transistors (FETs) in known DCC circuit topologies are replaced with linear resistors coupled to switches of the DCC circuit such that when the switch is open, the input signal is routed through the linear resistors. The linear resistors are more tolerant of process, voltage and temperature (PVT) fluctuations than FETs and thus, the resulting DCC circuit provides a relatively smaller change in DCC correction range with PVT fluctuations than the known DCC circuit topology that employs FETs. The linear resistors may be provided in parallel with the switches and in series with a pair of FETs having relatively large resistance values. The linear resistors provide resistance that pulls-up or pulls-down the pulse width of the input signal so as to provide correction to the duty cycle of the input signal.

公开(公告)号：US20070300113A1

公开(公告)日：2007-12-27

申请号：US11848314

申请日：2007-08-31

申请人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： G06F11/27

CPC分类号： H03K5/1565 ,  G01R31/31727 ,  G01R31/3187

摘要： An apparatus and method for automatically calibrating a duty cycle circuit for maximum performance are provided. A chip level built-in circuit that automatically calibrates the duty cycle correction (DCC) circuit setting for each chip is provided. This chip level built-in circuit includes a clock generation macro unit, a simple duty cycle correction (DCC) circuit, an array slice and built-in self test unit, and a DCC circuit controller. Results of a built-in self test, i.e. pass or fail, of an array are provided to the DCC circuit controller. If the result of the built-in self test is a pass, then the current DCC circuit controller's DCC control bit setting is set as the setting for the chip. If the result from the built-in self test is a fail, the DCC circuit controller's DCC control bits setting is incremented to a next setting and the self-test is performed again.

摘要翻译： 提供一种用于自动校准占空比电路以实现最大性能的装置和方法。 提供了自动校准每个芯片的占空比校正（DCC）电路设置的芯片级内置电路。 该芯片级内置电路包括时钟生成宏单元，简单占空比校正（DCC）电路，阵列片和内置自检单元以及DCC电路控制器。 向DCC电路控制器提供阵列的内置自检，即通过或失败的结果。 如果内置自检的结果是通过，则将当前DCC电路控制器的DCC控制位设置设置为芯片的设置。 如果内置自检的结果为失败，DCC电路控制器的DCC控制位设置将增加到下一个设置，并再次执行自检。

公开(公告)号：US20070266285A1

公开(公告)日：2007-11-15

申请号：US11381031

申请日：2006-05-01

申请人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： G01R31/28

CPC分类号： G01R31/31727

摘要： The disclosed methodology and apparatus measure the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. In one embodiment, the DCM circuit includes a capacitor driven by a charge pump. The reference clock signal drives the charge pump. The clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit applies a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. Control software accesses the data store to determine the duty cycle to which the test clock signal corresponds.

摘要翻译： 所公开的方法和装置测量时钟电路提供给占空比测量（DCM）电路的参考时钟信号的占空比。 在一个实施例中，DCM电路包括由电荷泵驱动的电容器。 参考时钟信号驱动电荷泵。 时钟电路在多个已知的占空比值之间改变参考时钟信号的占空比。 DCM电路将对应于每个已知占空比值的合成电容电压值存储在数据存储器中。 DCM电路通过电荷泵向电容器施加具有未知占空比的测试时钟信号，从而将电容器充电到对应于测试时钟信号占空比的新电压值。 控制软件访问数据存储，以确定测试时钟信号对应的占空比。

公开(公告)号：US07245161B2

公开(公告)日：2007-07-17

申请号：US11227026

申请日：2005-09-15

申请人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： H03K17/00

CPC分类号： G01R31/31708 ,  G01R31/31725

摘要： An apparatus and method for verifying glitch-free operation of a multiplexer are provided. The apparatus includes a circuit having a plurality of flip-flop elements that receive as inputs the plurality of clock signals that are inputs to the multiplexer, and a corresponding synchronized output signal of a decoder generated based on control inputs to the decoder. The synchronized output signals from the decoder are used as trigger signals to the plurality of flip-flops. The flip-flops sample the clock signals based upon the trigger signals and provide outputs to a logic gate. The logic gate operates on the outputs from the flip-flops to generate an output signal indicative of whether glitch-free operation is verified or is not verified.

摘要翻译： 提供一种用于验证多路复用器无毛刺操作的装置和方法。 该装置包括具有多个触发器元件的电路，多个触发器元件接收作为多路复用器的输入的多个时钟信号作为输入，以及基于对解码器的控制输入生成的解码器的对应的同步输出信号。 来自解码器的同步输出信号被用作到多个触发器的触发信号。 触发器根据触发信号对时钟信号进行采样，并向逻辑门提供输出。 逻辑门对来自触发器的输出进行操作，以产生指示无毛刺操作被验证或未被验证的输出信号。