中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

144 records (took 0.02 seconds)

    Automatic gain control using multi-comparators
    61.
    发明授权
    Automatic gain control using multi-comparators 失效
    使用多比较器进行自动增益控制

    公开(公告)号：US07456690B2

    公开(公告)日：2008-11-25

    申请号：US11135208

    申请日：2005-05-23

    Applicant: Namik Kemal Kocaman ,  Afshin Momtaz

    Inventor： Namik Kemal Kocaman ,  Afshin Momtaz

    IPC: H03G3/10

    CPC classification number: H03G3/3052 ,  H03G3/001 ,  H03G3/3036

    Abstract: A method and apparatus for an automatic gain control (AGC) loop that utilizes multiple comparators to provide constant bandwidth tracking and step response, as well as fine granularity for decision directed convergence. In one embodiment, an odd number of comparators is used with square-law scaling at the output to achieve constant bandwidth step response for a wide range of input amplitude changes.

    Abstract translation: 一种用于自动增益控制（AGC）回路的方法和装置，其利用多个比较器来提供恒定的带宽跟踪和阶跃响应，以及用于决策定向收敛的细粒度。 在一个实施例中，使用奇数比较器，在输出处使用平方律缩放来实现宽范围的输入幅度变化的恒定带宽阶跃响应。

    Fully differential CMOS phase-locked loop
    63.
    发明授权
    Fully differential CMOS phase-locked loop 有权
    全差分CMOS锁相环

    公开(公告)号：US07266172B2

    公开(公告)日：2007-09-04

    申请号：US10797770

    申请日：2004-03-10

    Applicant: Armond Hairapetian ,  Jun Cao ,  Afshin Momtaz

    Inventor： Armond Hairapetian ,  Jun Cao ,  Afshin Momtaz

    IPC: H03L7/08 ,  H03L7/089

    CPC classification number: H03L7/18 ,  H03L7/089 ,  H03L7/099

    Abstract: The present invention relates in general to integrated circuits, and in particular to method and circuitry for implementing an improved phase-locked loop (PLL) in complementary metal-oxide-semiconductor (CMOS)technology using current-controlled CMOS (C3MOS) logic. In an exemplary embodiment, a phase-locked loop includes a phase-frequency detector, a Gm cell block, a low pass filter and a voltage controlled oscillator. These various elements of the phase-locked loop are connected to one another in a fully differential manner, i.e., each element has an input and/or an output each having at least a differential signal. In one embodiment, each of these various elements of the phase-locked loop is implemented using C3MOS logic.

    Abstract translation: 本发明一般涉及集成电路，特别涉及用于使用电流控制CMOS（C 3）来实现使用互补金属氧化物半导体（CMOS）技术的改进的锁相环（PLL）的方法和电路 MOS）逻辑。 在示例性实施例中，锁相环包括相位频率检测器，Gm单元块，低通滤波器和压控振荡器。 锁相环的这些各种元件以完全差分的方式相互连接，即每个元件具有至少具有差分信号的输入和/或输出。 在一个实施例中，使用C 3 MOS逻辑来实现锁相环的这些各种元件中的每一个。

    High frequency loss of signal detector
    64.
    发明授权
    High frequency loss of signal detector 失效
    信号检测器的高频损耗

    公开(公告)号：US07263151B2

    公开(公告)日：2007-08-28

    申请号：US10092166

    申请日：2002-03-04

    Applicant: Afshin Momtaz ,  Pang-Cheng Hsu

    Inventor： Afshin Momtaz ,  Pang-Cheng Hsu

    IPC: H04L7/00 ,  G01R29/00 ,  H03K9/08 ,  H03L7/00

    CPC classification number: H04L1/20 ,  H04L7/0083

    Abstract: Methods and circuitry for implementing high speed loss-of-signal detectors for use in Gb/s telecommunication applications. The invention measures bit error rate (BER) of the incoming data by comparing the phase of the clock signal extracted from the incoming data with that of a delayed version of the incoming data. The results of this comparison are averaged over time to arrive at the BER. The measured BER is compared to a predetermined threshold value to detect a loss-of-signal condition. The invention adjusts the amount of delay of the incoming data in such a manner as to minimize the capacitive loading on the data line and clock line introduced by the loss-of-signal circuitry.

    Abstract translation: 用于实现用于Gb / s电信应用的高速信号丢失信号检测器的方法和电路。 本发明通过比较从输入数据提取的时钟信号的相位与输入数据的延迟版本的相位来测量输入数据的误码率（BER）。 该比较的结果随时间平均以达到BER。 将测量的BER与预定阈值进行比较，以检测信号丢失状况。 本发明以使信号丢失信号电路引入的数据线和时钟线上的容性负载最小化的方式来调整输入数据的延迟量。

    Automatic gain control with three states of operation
    65.
    发明申请
    Automatic gain control with three states of operation 失效

    公开(公告)号：US20070188236A1

    公开(公告)日：2007-08-16

    申请号：US11729587

    申请日：2007-03-29

    Applicant: Namik Kocaman ,  Afshin Momtaz

    Inventor： Namik Kocaman ,  Afshin Momtaz

    IPC: H03G3/10

    CPC classification number: H03F3/45973 ,  H03F2200/435 ,  H03F2200/78 ,  H03G3/001 ,  H03G3/30

    Abstract: A method and apparatus for an automatic gain control (AGC) loop that utilizes freezing and unfreezing states. A freezing process moves the AGC into a TRANSITION state from a NORMAL state, based on net change of VGA gain control codes over a monitoring time window. The freezing process then moves the AGC into a FROZEN state from the TRANSITION state, based on net change of VGA gain control codes over the monitoring time window. An unfreezing process moves the AGC into the NORMAL state from the FROZEN state, based on signal amplitude changes at the output of the VGA.

    High frequency binary phase detector
    66.
    发明授权
    High frequency binary phase detector 有权
    高频二进制相位检测器

    公开(公告)号：US07202707B2

    公开(公告)日：2007-04-10

    申请号：US10776074

    申请日：2004-02-11

    Applicant: Afshin Momtaz

    Inventor： Afshin Momtaz

    IPC: G01R25/00

    CPC classification number: H03D13/003

    Abstract: A phase detector includes a first flip flop having a data input coupled to a first clock signal at a first frequency and a clock input coupled to a second clock signal at a second frequency. The frequency of the first clock signal is a multiple of the frequency of the second clock signal. The phase detector also includes a second flip flop having a data input coupled to an output of the first flip flop and a clock input coupled to the second clock signal.

    Abstract translation: 相位检测器包括第一触发器，其具有耦合到第一频率的第一时钟信号的数据输入和以第二频率耦合到第二时钟信号的时钟输入。 第一时钟信号的频率是第二时钟信号的频率的倍数。 相位检测器还包括具有耦合到第一触发器的输出的数据输入和耦合到第二时钟信号的时钟输入的第二触发器。

    Automatic gain control with three states of operation
    68.
    发明申请
    Automatic gain control with three states of operation 有权
    具有三种运行状态的自动增益控制

    公开(公告)号：US20060238255A1

    公开(公告)日：2006-10-26

    申请号：US11112041

    申请日：2005-04-22

    Applicant: Namik Kocaman ,  Afshin Momtaz

    Inventor： Namik Kocaman ,  Afshin Momtaz

    IPC: H03G3/10

    CPC classification number: H03F3/45973 ,  H03F2200/435 ,  H03F2200/78 ,  H03G3/001 ,  H03G3/30

    Abstract: A method and apparatus for an automatic gain control (AGC) loop that utilizes freezing and unfreezing states. A freezing process moves the AGC into a TRANSITION state from a NORMAL state, based on net change of VGA gain control codes over a monitoring time window. The freezing process then moves the AGC into a FROZEN state from the TRANSITION state, based on net change of VGA gain control codes over the monitoring time window. An unfreezing process moves the AGC into the NORMAL state from the FROZEN state, based on signal amplitude changes at the output of the VGA.

    Abstract translation: 一种利用冷冻和解​​冻状态的自动增益控制（AGC）回路的方法和装置。 基于监视时间窗口的VGA增益控制代码的净变化，冻结过程将AGC从NORMAL状态移动到TRANSITION状态。 基于监视时间窗口的VGA增益控制代码的净变化，冷冻过程然后将AGC从TRANSITION状态移动到FROZEN状态。 基于VGA输出端的信号幅度变化，解冻过程将AGC从FROZEN状态移动到NORMAL状态。

    High speed peak amplitude comparator
    69.
    发明申请
    High speed peak amplitude comparator 审中-公开

    公开(公告)号：US20060208768A1

    公开(公告)日：2006-09-21

    申请号：US11438405

    申请日：2006-05-22

    Applicant: Afshin Momtaz ,  Wee-Guan Tan ,  Armond Hairapetian

    Inventor： Afshin Momtaz ,  Wee-Guan Tan ,  Armond Hairapetian

    IPC: H03K5/153

    CPC classification number: H03K5/1532 ,  G01R19/04 ,  G01R19/16585

    Abstract: Various methods and circuits for implementing high speed peak amplitude comparison. The invention achieves higher speed of operation by eliminating the slow feedback loop commonly employed in peak detection. In one embodiment, the invention directly compares a signal that represents the peak amplitude of the input signal minus a small voltage drop, to a modified reference voltage. The modified reference voltage corresponds to the reference voltage that is adjusted to compensate for the small voltage drop in the maximum input voltage. In another embodiment, the invention implements a differential version of the peak amplitude comparator to obtain better noise rejection and reduced effective offset among other advantages.

    High speed peak amplitude comparator
    70.
    发明申请
    High speed peak amplitude comparator 审中-公开

    公开(公告)号：US20060164127A1

    公开(公告)日：2006-07-27

    申请号：US11369604

    申请日：2006-03-06

    Applicant: Afshin Momtaz ,  Wee-Guan Tan ,  Almond Hairapetian

    Inventor： Afshin Momtaz ,  Wee-Guan Tan ,  Almond Hairapetian

    IPC: H03K5/153

    CPC classification number: H03K5/1532 ,  G01R19/04

    Abstract: Various methods and circuits for implementing high speed peak amplitude comparison. The invention achieves higher speed of operation by eliminating the slow feedback loop commonly employed in peak detection. In one embodiment, the invention directly compares a signal that represents the peak amplitude of the input signal minus a small voltage drop, to a modified reference voltage. The modified reference voltage corresponds to the reference voltage that is adjusted to compensate for the small voltage drop in the maximum input voltage. In another embodiment, the invention implements a differential version of the peak amplitude comparator to obtain better noise rejection and reduced effective offset among other advantages.

Patent Agency Ranking