公开(公告)号：US08225417B2

公开(公告)日：2012-07-17

申请号：US12170206

申请日：2008-07-09

申请人： Kwang-Myoung Rho ,  Jae-Jin Lee

发明人： Kwang-Myoung Rho ,  Jae-Jin Lee

IPC分类号： G06F1/26

CPC分类号： G11C7/1078 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1084 ,  H03K19/018521

摘要： A circuit for controlling a signal line transmitting data. The circuit includes a data level controller that, when the level of the data transmitted through the signal line is changed, controls the level of the data to be lower than an external power supply voltage level and higher than a ground voltage level after a predetermined time.

摘要翻译： 用于控制发送数据的信号线的电路。 该电路包括数据电平控制器，当通过信号线传输的数据的电平改变时，数据电平低于外部电源电压并且在预定时间之后高于接地电压电平 。

公开(公告)号：US20110075491A1

公开(公告)日：2011-03-31

申请号：US12648983

申请日：2009-12-29

申请人： Tae-Sik Yun ,  Jae-Jin Lee

发明人： Tae-Sik Yun ,  Jae-Jin Lee

IPC分类号： G11C7/00 ,  G11C7/02 ,  G11C5/14

CPC分类号： G11C11/4091 ,  G11C5/147

摘要： Disclosed is a semiconductor memory apparatus which improves the time to transmit write data to a memory cell and improves data retention time of the memory cell. To this end, the semiconductor memory apparatus includes a bit-line sense amplifier that senses and amplifies data of bit-line pairs by driving power supplied through a pull up power line and a pull down power line and transmits the amplified data to a memory cell. A bit-line sense amplification power supply unit supplies pull up driving voltage and pull down driving voltage to the pull up and pull down power lines in an active mode and supplies an over driving voltage and the pull down driving voltage having a higher voltage level than the pull up driving voltage to the pull up and pull down power lines until the memory cell is deactivated in a precharge mode.

摘要翻译： 公开了一种半导体存储装置，其改善了将数据写入存储单元的时间，并且提高了存储单元的数据保持时间。 为此，半导体存储装置包括：位线读出放大器，其通过驱动通过上拉电力线和下拉电力线提供的电力来感测和放大位线对的数据，并将放大的数据发送到存储单元 。 位线检测放大电源单元提供上拉驱动电压并将驱动电压下拉至上拉电源线并将其下拉至主动模式，并提供过驱动电压和下拉驱动电压，具有比 上拉驱动电压上拉并下拉电源线，直到存储单元在预充电模式下被禁用。

公开(公告)号：US07826583B2

公开(公告)日：2010-11-02

申请号：US11819807

申请日：2007-06-29

申请人： Chun-Seok Jeong ,  Jae-Jin Lee ,  Chang-Sik Yoo ,  Jung-June Park ,  Young-Suk Seo

发明人： Chun-Seok Jeong ,  Jae-Jin Lee ,  Chang-Sik Yoo ,  Jung-June Park ,  Young-Suk Seo

IPC分类号： H03D3/24 ,  H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC分类号： H03D13/004

摘要： A clock data recovery apparatus includes a phase looked loop unit, a voltage control delay line, a phase detection unit, a charge pump unit, and a loop filter unit. The phase looked loop unit outputs a plurality of clock signals which are different from each other in phase and of which frequency is lower than that of data. The voltage control delay line outputs recovered clock signals by delaying the clock signals according to input voltage levels. The phase detection unit outputs recovered data in synchronization with the clock signals, respectively and outputs increment and decrement signals which have wider pulse width than the data by comparing the recovered clock signals with the data. The charge pump unit outputs a corresponding current in response to the increment and decrement signals. The loop filter unit determines an amount of delay in the voltage control delay line by outputting the voltage.

摘要翻译： 时钟数据恢复装置包括相位循环单元，电压控制延迟线，相位检测单元，电荷泵单元和环路滤波器单元。 相位循环单元输出相位不同的多个时钟信号，其频率低于数据的时钟信号。 电压控制延迟线通过根据输入电压电平延迟时钟信号来输出恢复的时钟信号。 相位检测单元分别与时钟信号同步地输出恢复的数据，并通过将恢复的时钟信号与数据进行比较，输出比数据宽的脉冲宽度的增减信号。 电荷泵单元响应于增量和减量信号输出相应的电流。 环路滤波器单元通过输出电压来确定电压控制延迟线中的延迟量。

公开(公告)号：US20100053504A1

公开(公告)日：2010-03-04

申请号：US12355993

申请日：2009-01-19

申请人： Dae-Won KIim ,  Kyung-Nam Kim ,  Jae-Jin Lee

发明人： Dae-Won KIim ,  Kyung-Nam Kim ,  Jae-Jin Lee

IPC分类号： G02F1/13357

CPC分类号： G02F1/133615 ,  G02B6/0073 ,  G02F1/133617

摘要： A backlight assembly includes a light guide plate and a light-emitting module. The light guide plate guides light. The light-emitting module is disposed to face an incidence surface of the light guide plate. The light-emitting module includes a printed circuit board (PCB) vertically disposed to face the incidence surface and a plurality of LEDs mounted on the PCB to emit light toward the incidence surface. Each of the LEDs includes a blue chip emitting blue light, a red fluorescent substance and a green fluorescent substance for converting the blue light into white light. Therefore, a thickness of the backlight assembly is reduced and an LED-mounting stability of the LED is improved.

摘要翻译： 背光组件包括导光板和发光模块。 导光板引导灯。 发光模块设置成面对导光板的入射表面。 发光模块包括垂直设置为面对入射表面的印刷电路板（PCB）和安装在PCB上的多个LED以朝向入射表面发光。 每个LED包括发出蓝光的蓝色芯片，红色荧光物质和用于将蓝色光转换成白色光的绿色荧光物质。 因此，背光组件的厚度减小，LED的LED安装稳定性提高。

公开(公告)号：US07514986B2

公开(公告)日：2009-04-07

申请号：US12027089

申请日：2008-02-06

申请人： Kang-Seol Lee ,  Jae-Jin Lee

发明人： Kang-Seol Lee ,  Jae-Jin Lee

IPC分类号： G05F1/10

CPC分类号： G11C5/145

摘要： The present invention provides voltage supplier for supplying an internal voltage with optimized drivability required for internal operation. The voltage supplier of a semiconductor memory device includes: an internal voltage detection means for detecting a voltage level of an internal voltage; a clock oscillation means for outputting a charge pumping clock signal; an internal voltage control means for controlling the clock oscillation means to be performed selectively in accordance with a data access mode or a non-data access mode; and a charge pumping means for outputting the internal voltage required for internal operation by pumping charges in response to the charge pumping clock signal.

摘要翻译： 本发明提供了一种内部电压提供内部操作所需的最佳驾驶性能的电压供应器。 半导体存储器件的电压供应器包括：内部电压检测装置，用于检测内部电压的电压电平; 时钟振荡装置，用于输出电荷泵送时钟信号; 内部电压控制装置，用于根据数据存取模式或非数据存取模式选择性地控制时钟振荡装置; 以及电荷泵送装置，用于响应于电荷泵送时钟信号，通过泵送电荷来输出内部操作所需的内部电压。

公开(公告)号：US07508332B2

公开(公告)日：2009-03-24

申请号：US11819795

申请日：2007-06-29

申请人： Chun-Seok Jeong ,  Jae-Jin Lee

发明人： Chun-Seok Jeong ,  Jae-Jin Lee

IPC分类号： H03M1/34

CPC分类号： G01K7/015 ,  G01K7/425 ,  H03M1/005 ,  H03M1/0863 ,  H03M1/109 ,  H03M1/40 ,  H03M1/46

摘要： An On Die Thermal Sensor (ODTS) of a semiconductor memory device includes: a temperature detector for detecting an internal temperature of the semiconductor memory device to generate a temperature voltage corresponding to the detected internal temperature; a tracking ADC for outputting a digital code by comparing the temperature voltage with a tracking voltage and performing a counting operation to the result of comparison; and an operation controller for controlling operations of the temperature detector and the analog-to-digital converter, wherein the tracking ADC performs the counting operation using a first tracking scheme having a relatively large unit variation width of the digital code value during an initial tracking period and a second tracking scheme having a relatively small unit variation width of the digital code value after the initial tracking period.

摘要翻译： 半导体存储器件的散热片传感器（ODTS）包括：温度检测器，用于检测半导体存储器件的内部温度以产生对应于检测到的内部温度的温度电压; 跟踪ADC，用于通过将温度电压与跟踪电压进行比较来输出数字代码，并对比较结果执行计数操作; 以及用于控制温度检测器和模数转换器的操作的操作控制器，其中跟踪ADC使用在初始跟踪周期期间具有数字码值的相对大的单位变化宽度的第一跟踪方案来执行计数操作 以及在初始跟踪周期之后具有数字码值的相对小的单位变化宽度的第二跟踪方案。

公开(公告)号：US20080211534A1

公开(公告)日：2008-09-04

申请号：US11967659

申请日：2007-12-31

申请人： Chun-Seok JEONG ,  Jae-Jin Lee

发明人： Chun-Seok JEONG ,  Jae-Jin Lee

IPC分类号： H03K17/16

CPC分类号： H03K19/0005 ,  G11C5/063 ,  G11C7/1048 ,  G11C2207/2254

摘要： An impedance matching circuit of a semiconductor memory device performs a ZQ calibration with initial values that reflect an offset error according to variations in a manufacturing process. The impedance matching circuit includes a first pull-down resistance unit, a first pull-up resistance unit, and a code generation unit. The first pull-down resistance unit supplies a ground voltage to a first node, thereby determining an initial pull-down code. The first pull-up resistance unit supplies a supply voltage to the first node, thereby determining an initial pull-up code or a voltage level on the first node. The code generation unit generates pull-down and pull-up calibration codes using the initial pull-down and pull-up codes as respective initial values.

摘要翻译： 半导体存储器件的阻抗匹配电路根据制造过程中的变化，以反映偏移误差的初始值来执行ZQ校准。 阻抗匹配电路包括第一下拉电阻单元，第一上拉电阻单元和代码生成单元。 第一下拉电阻单元向第一节点提供接地电压，从而确定初始下拉代码。 第一上拉电阻单元向第一节点提供电源电压，从而确定第一节点上的初始上拉代码或电压电平。 代码生成单元使用初始下拉和上拉代码作为相应的初始值生成下拉和上拉校准代码。

公开(公告)号：US20080181037A1

公开(公告)日：2008-07-31

申请号：US12072548

申请日：2008-02-26

申请人： Chang-Ho Do ,  Jae-Jin Lee

发明人： Chang-Ho Do ,  Jae-Jin Lee

IPC分类号： G11C29/00 ,  G11C8/00

CPC分类号： G11C29/26 ,  G11C8/16

摘要： A semiconductor memory device includes: a plurality of ports configured to perform a serial input/output (I/O) data communication with external devices; a plurality of banks configured to perform a parallel I/O data communication with the ports; a global data bus configured to transmit a signal between the banks and the ports; a test mode determiner configured to determine an operation mode of the semiconductor memory device by generating a test mode enable signal in response to a test mode control signal; a test I/O controller configured to transmit and receive a test signal with the ports in response to the test mode enable signal during a port test mode; and a plurality of selectors, each of which is configured to receive the test signal output from the corresponding port in series and feedback the test signal to the corresponding port.

摘要翻译： 半导体存储器件包括：多个端口，被配置为执行与外部设备的串行输入/输出（I / O）数据通信; 配置为执行与所述端口的并行I / O数据通信的多个存储体; 全局数据总线，被配置为在所述存储体和所述端口之间传输信号; 测试模式确定器，被配置为通过响应于测试模式控制信号产生测试模式使能信号来确定半导体存储器件的操作模式; 测试I / O控制器，被配置为在端口测试模式期间响应于测试模式使能信号在端口上发送和接收测试信号; 以及多个选择器，每个选择器被配置为从串行的相应端口接收输出的测试信号，并将测试信号反馈到相应的端口。

公开(公告)号：US20080101524A1

公开(公告)日：2008-05-01

申请号：US11819807

申请日：2007-06-29

申请人： Chun-Seok Jeong ,  Jae-Jin Lee ,  Chang-Sik Yoo ,  Jung-June Park ,  Young-Suk Seo

发明人： Chun-Seok Jeong ,  Jae-Jin Lee ,  Chang-Sik Yoo ,  Jung-June Park ,  Young-Suk Seo

IPC分类号： H03D3/24

CPC分类号： H03D13/004

摘要： A clock data recovery apparatus includes a phase looked loop unit, a voltage control delay line, a phase detection unit, a charge pump unit, and a loop filter unit. The phase looked loop unit outputs a plurality of clock signals which are different from each other in phase and of which frequency is lower than that of data. The voltage control delay line outputs recovered clock signals by delaying the clock signals according to input voltage levels. The phase detection unit outputs recovered data in synchronization with the clock signals, respectively and outputs increment and decrement signals which have wider pulse width than the data by comparing the recovered clock signals with the data. The charge pump unit outputs a corresponding current in response to the increment and decrement signals. The loop filter unit determines an amount of delay in the voltage control delay line by outputting the voltage.

摘要翻译： 时钟数据恢复装置包括相位循环单元，电压控制延迟线，相位检测单元，电荷泵单元和环路滤波器单元。 相位循环单元输出相位不同的多个时钟信号，其频率低于数据的时钟信号。 电压控制延迟线通过根据输入电压电平延迟时钟信号来输出恢复的时钟信号。 相位检测单元分别与时钟信号同步地输出恢复的数据，并通过将恢复的时钟信号与数据进行比较，输出比数据宽的脉冲宽度的增减信号。 电荷泵单元响应于增量和减量信号输出相应的电流。 环路滤波器单元通过输出电压来确定电压控制延迟线中的延迟量。

公开(公告)号：US07349272B2

公开(公告)日：2008-03-25

申请号：US11541236

申请日：2006-09-28

申请人： Chang-Ho Do ,  Jae-Jin Lee

发明人： Chang-Ho Do ,  Jae-Jin Lee

IPC分类号： G11C11/00

CPC分类号： G11C29/26 ,  G11C8/16

摘要： A semiconductor memory device includes: a plurality of ports configured to perform a serial input/output (I/O) data communication with external devices; a plurality of banks configured to perform a parallel I/O data communication with the ports; a global data bus configured to transmit a signal between the banks and the ports; a test mode determiner configured to determine an operation mode of the semiconductor memory device by generating a test mode enable signal in response to a test mode control signal; a test I/O controller configured to transmit and receive a test signal with the ports in response to the test mode enable signal during a port test mode; and a plurality of selectors, each of which is configured to receive the test signal output from the corresponding port in series and feedback the test signal to the corresponding port.