公开(公告)号：US08339872B2

公开(公告)日：2012-12-25

申请号：US12648983

申请日：2009-12-29

申请人： Tae-Sik Yun ,  Jae-Jin Lee

发明人： Tae-Sik Yun ,  Jae-Jin Lee

IPC分类号： G11C7/00 ,  G11C7/02 ,  G11C5/14

CPC分类号： G11C11/4091 ,  G11C5/147

摘要： Disclosed is a semiconductor memory apparatus which improves the time to transmit write data to a memory cell and improves data retention time of the memory cell. To this end, the semiconductor memory apparatus includes a bit-line sense amplifier that senses and amplifies data of bit-line pairs by driving power supplied through a pull up power line and a pull down power line and transmits the amplified data to a memory cell. A bit-line sense amplification power supply unit supplies pull up driving voltage and pull down driving voltage to the pull up and pull down power lines in an active mode and supplies an over driving voltage and the pull down driving voltage having a higher voltage level than the pull up driving voltage to the pull up and pull down power lines until the memory cell is deactivated in a precharge mode.

摘要翻译： 公开了一种半导体存储装置，其改善了将数据写入存储单元的时间，并且提高了存储单元的数据保持时间。 为此，半导体存储装置包括：位线读出放大器，其通过驱动通过上拉电力线和下拉电力线提供的电力来感测和放大位线对的数据，并将放大的数据发送到存储单元 。 位线检测放大电源单元提供上拉驱动电压并将驱动电压下拉至上拉电源线并将其下拉至主动模式，并提供过驱动电压和下拉驱动电压，具有比 上拉驱动电压上拉并下拉电源线，直到存储单元在预充电模式下被禁用。

公开(公告)号：US20110075491A1

公开(公告)日：2011-03-31

申请号：US12648983

申请日：2009-12-29

申请人： Tae-Sik Yun ,  Jae-Jin Lee

发明人： Tae-Sik Yun ,  Jae-Jin Lee

IPC分类号： G11C7/00 ,  G11C7/02 ,  G11C5/14

CPC分类号： G11C11/4091 ,  G11C5/147

摘要： Disclosed is a semiconductor memory apparatus which improves the time to transmit write data to a memory cell and improves data retention time of the memory cell. To this end, the semiconductor memory apparatus includes a bit-line sense amplifier that senses and amplifies data of bit-line pairs by driving power supplied through a pull up power line and a pull down power line and transmits the amplified data to a memory cell. A bit-line sense amplification power supply unit supplies pull up driving voltage and pull down driving voltage to the pull up and pull down power lines in an active mode and supplies an over driving voltage and the pull down driving voltage having a higher voltage level than the pull up driving voltage to the pull up and pull down power lines until the memory cell is deactivated in a precharge mode.

摘要翻译： 公开了一种半导体存储装置，其改善了将数据写入存储单元的时间，并且提高了存储单元的数据保持时间。 为此，半导体存储装置包括：位线读出放大器，其通过驱动通过上拉电力线和下拉电力线提供的电力来感测和放大位线对的数据，并将放大的数据发送到存储单元 。 位线检测放大电源单元提供上拉驱动电压并将驱动电压下拉至上拉电源线并将其下拉至主动模式，并提供过驱动电压和下拉驱动电压，具有比 上拉驱动电压上拉并下拉电源线，直到存储单元在预充电模式下被禁用。

公开(公告)号：US08743644B2

公开(公告)日：2014-06-03

申请号：US13547582

申请日：2012-07-12

申请人： Sang-Mook Oh ,  Tae-Sik Yun

发明人： Sang-Mook Oh ,  Tae-Sik Yun

IPC分类号： G11C17/18 ,  G11C29/00 ,  G11C29/02

CPC分类号： G11C29/027 ,  G11C17/16 ,  G11C17/18 ,  G11C29/02 ,  G11C29/785 ,  G11C29/787 ,  G11C29/838 ,  G11C2029/0407

摘要： A semiconductor integrated circuit includes: a normal fuse cell array programmed with a normal fuse data; a dummy fuse cell array programmed with a verifying fuse data; and a sensor configured to read the verifying fuse data from the dummy fuse cell array and read the normal fuse data from the normal fuse cell array, wherein the normal fuse cell array is configured to be read according to a reading result of the dummy fuse cell array.

摘要翻译： 半导体集成电路包括：用正常熔丝数据编程的正常熔丝单元阵列; 用验证熔丝数据编程的虚拟熔丝单元阵列; 以及传感器，被配置为从虚拟熔丝单元阵列读取验证熔丝数据，并从正常熔丝单元阵列中读出常规熔丝数据，其中，根据虚拟熔丝单元的读取结果，配置正常熔丝单元阵列 数组。

公开(公告)号：US08591809B2

公开(公告)日：2013-11-26

申请号：US13048153

申请日：2011-03-15

申请人： Byung-Koog Ra ,  Tae-Sik Yun ,  Kunhyung Lee ,  Hyunjoon Kim ,  Hyeogki Kim ,  KiDoo Kim

发明人： Byung-Koog Ra ,  Tae-Sik Yun ,  Kunhyung Lee ,  Hyunjoon Kim ,  Hyeogki Kim ,  KiDoo Kim

IPC分类号： G01N21/00 ,  G01N31/00 ,  G01N33/00 ,  G06F11/30 ,  G21C17/00 ,  B65B1/30 ,  B65B3/26 ,  B65B1/04 ,  B65B3/04 ,  B67C3/02 ,  H01L21/20 ,  H01L21/36 ,  C23C16/24

CPC分类号： H01L21/67376 ,  H01L21/67389

摘要： A substrate transfer container comprises a housing including a plurality of substrate slots positioned within a gas chamber having an interior environment. Each substrate slot accommodates a substrate undergoing a substrate manufacturing process, the interior environment of the gas chamber being selectively sealed from an exterior environment. A detection unit at the housing is constructed and arranged to detect an environmental property of the interior environment of the gas chamber, and to generate a detection signal in response. A signal transmission module at the housing is configured to wirelessly transmit a detection signal received from the detection unit.

摘要翻译： 衬底转移容器包括壳体，该壳体包括位于具有内部环境的气体室内的多个衬底狭槽。 每个衬底槽容纳经历衬底制造工艺的衬底，气体室的内部环境与外部环境选择性地密封。 壳体上的检测单元被构造和布置成检测气室的内部环境的环境特性，并且响应地产生检测信号。 在壳体处的信号传输模块被配置为无线地发送从检测单元接收到的检测信号。

公开(公告)号：US07835180B2

公开(公告)日：2010-11-16

申请号：US12347520

申请日：2008-12-31

申请人： Tae-Sik Yun

发明人： Tae-Sik Yun

IPC分类号： G11C11/34

CPC分类号： G11C8/12 ,  G11C8/04 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4097

摘要： A semiconductor memory device includes a plurality of banks, each configured to receive a bank operation control signal and perform predetermined operations in response to the received bank operation control signal, a plurality of bank control blocks, each configured to receive a bank sequential signal and generate the plurality of bank operation control signals in response to enable periods of the received bank sequential signal, and a bank sequential signal generating block configured to generate the plurality of bank sequential signals each having a multiplicity of enable periods that are sequential in response to a command signal.

摘要翻译： 半导体存储器件包括多个存储体，每个存储体被配置为接收存储体操作控制信号并且响应于所接收的存储体操作控制信号执行预定操作，多个存储体控制块，每个存储体控制块被配置为接收存储体顺序信号并产生 所述多个存储体操作控制信号响应于所接收的存储体顺序信号的使能周期，以及存储体顺序信号生成模块，其被配置为生成所述多个存储体顺序信号，每一组具有多个响应于命令的顺序的使能周期 信号。

公开(公告)号：US07619937B2

公开(公告)日：2009-11-17

申请号：US11819819

申请日：2007-06-29

申请人： Tae-Sik Yun ,  Kee-Teok Park

发明人： Tae-Sik Yun ,  Kee-Teok Park

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C7/1078 ,  G11C7/109 ,  G11C7/20 ,  G11C29/1201 ,  G11C29/46

摘要： A semiconductor memory device performs a reset operation at a wafer state by using a signal input through an address pin in a test mode. The semiconductor memory device includes a buffer for transferring a reset command in response to a reset-active signal and a test reset signal, a test-reset entry signal generation unit for generating an internal test-reset entry signal in response to the test reset signal, and a rest signal driving unit for driving an active signal of an output signal of the buffer and the internal test-reset entry signal as an internal reset signal for a reset mode entry.

摘要翻译： 半导体存储器件通过在测试模式下通过地址引脚输入的信号在晶片状态下执行复位操作。 半导体存储器件包括用于响应于复位有效信号和测试复位信号传送复位指令的缓冲器，用于响应于测试复位信号产生内部测试复位输入信号的测试复位输入信号产生单元 以及用于驱动缓冲器的输出信号的有效信号和内部测试复位输入信号的休息信号驱动单元作为复位模式输入的内部复位信号。

公开(公告)号：US20130162315A1

公开(公告)日：2013-06-27

申请号：US13619632

申请日：2012-09-14

申请人： Sang-Mook Oh ,  Tae-Sik Yun

发明人： Sang-Mook Oh ,  Tae-Sik Yun

IPC分类号： H03H11/26

CPC分类号： H04B3/36

摘要： A signal transmission/reception system includes a transmission line, a signal transmission circuit configured to generate a transfer signal and transfer the transfer signal through the transmission line, wherein a logic value of the transfer signal is changed whenever a pulse signal is input to the signal transmission circuit, and a signal reception circuit configured to receive the transfer signal through the transmission line and generate a restoration signal using the transfer signal and a delayed transfer signal obtained by delaying the transfer signal.

摘要翻译： 信号发送/接收系统包括传输线，信号传输电路，被配置为产生传送信号并通过传输线传送传送信号，其中每当将脉冲信号输入到信号时传送信号的逻辑值改变 发送电路和信号接收电路，被配置为通过传输线接收传送信号，并使用传送信号和通过延迟传送信号获得的延迟传送信号产生恢复信号。

公开(公告)号：US08441831B2

公开(公告)日：2013-05-14

申请号：US12878347

申请日：2010-09-09

申请人： Young-Jun Ku ,  Tae-Sik Yun

发明人： Young-Jun Ku ,  Tae-Sik Yun

IPC分类号： G11C5/06

CPC分类号： H01L23/522 ,  G06F2213/0038 ,  H01L23/481 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/0002 ,  H04J3/047 ,  H04L25/028 ,  H04L25/0292 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor integrated circuit includes a first semiconductor chip including a first output circuit which is enabled in a first operation mode and outputs a first output signal and a second output circuit which is enabled in a second operation mode and outputs a second output signal; a second semiconductor chip including a first input circuit which is enabled in the first operation mode and receives the first output signal and a second input circuit which is enabled in the second operation mode and receives the second output signal; and a common through chip via arranged to vertically penetrate through the semiconductor chip, be coupled with the first and second output circuits in one end and coupled with the first and second input circuits in the other end, and interface transfer of the first and second output signals which are enabled in different operation modes, including the first and second operation modes.

摘要翻译： 一种半导体集成电路包括：第一半导体芯片，包括第一输出电路，其在第一操作模式下使能并输出第一输出信号;以及第二输出电路，其在第二操作模式下被使能并输出第二输出信号; 第二半导体芯片，包括在第一操作模式中被使能并接收第一输出信号的第一输入电路和在第二操作模式中被使能并接收第二输出信号的第二输入电路; 并且布置成垂直穿过半导体芯片的通用芯片通孔在一端与第一和第二输出电路耦合，并在另一端与第一和第二输入电路耦合，并且第一和第二输出 在不同的操作模式下启用的信号，包括第一和第二操作模式。

公开(公告)号：US20110220545A1

公开(公告)日：2011-09-15

申请号：US13048153

申请日：2011-03-15

申请人： Byung-Koog Ra ,  Tae-Sik Yun ,  Kunhyung Lee ,  Hyunjoon Kim ,  Hyeogki Kim ,  KiDoo Kim

发明人： Byung-Koog Ra ,  Tae-Sik Yun ,  Kunhyung Lee ,  Hyunjoon Kim ,  Hyeogki Kim ,  KiDoo Kim

IPC分类号： B65D85/86

CPC分类号： H01L21/67376 ,  H01L21/67389

摘要： A substrate transfer container comprises a housing including a plurality of substrate slots positioned within a gas chamber having an interior environment. Each substrate slot accommodates a substrate undergoing a substrate manufacturing process, the interior environment of the gas chamber being selectively sealed from an exterior environment. A detection unit at the housing is constructed and arranged to detect an environmental property of the interior environment of the gas chamber, and to generate a detection signal in response. A signal transmission module at the housing is configured to wirelessly transmit a detection signal received from the detection unit.

摘要翻译： 衬底转移容器包括壳体，该壳体包括位于具有内部环境的气体室内的多个衬底狭槽。 每个衬底槽容纳经历衬底制造工艺的衬底，气体室的内部环境与外部环境选择性地密封。 壳体上的检测单元被构造和布置成检测气室的内部环境的环境特性，并且响应地产生检测信号。 在壳体处的信号传输模块被配置为无线地发送从检测单元接收到的检测信号。

公开(公告)号：US20100061177A1

公开(公告)日：2010-03-11

申请号：US12344629

申请日：2008-12-29

申请人： Tae-Sik Yun ,  Kang-Seol Lee

发明人： Tae-Sik Yun ,  Kang-Seol Lee

IPC分类号： G11C8/00 ,  G11C8/08

CPC分类号： G11C8/10 ,  G11C8/08

摘要： A semiconductor memory device having a plurality of cell blocks includes: a block decoding unit configured to decode an input address for selecting a corresponding cell block to generate a block selection signal; a block information address generating unit configured to perform a logic operation on the block selection signal and an assignment address for selecting a word line to be activated within the corresponding cell block to generate a block information address activated only when the corresponding cell block is selected; and a word line driving unit configured to select a word line in response to the block information address.

摘要翻译： 具有多个单元块的半导体存储器件包括：块解码单元，被配置为对用于选择相应的单元块的输入地址进行解码以产生块选择信号; 块信息地址生成单元，被配置为对块选择信号执行逻辑运算，以及分配地址，用于选择要在相应的单元块内激活的字线，以产生只有当相应的单元块被选择时激活的块信息地址; 以及字线驱动单元，被配置为响应于块信息地址来选择字线。