摘要:
The present invention relates to methods and apparatus for improving the stability of static random access memory (SRAM) cells by using boosted word lines. Specifically, a boosted word line voltage (Vdd′) is applied to the word line of a selected SRAM cell, while such a boosted word line voltage (Vdd′) is sufficiently higher than the power supply voltage (Vdd) of the SRAM cell so as to improve the cell stability to a desired level. Specifically, a specific boosted word line voltage is predetermined for each SRAM cell based on the specific cell configuration, by using a circuit simulation program, such as the BERKELEY-SPICE simulation program. A boost voltage generator is then used to apply the predetermined boosted word line voltage to the selected SRAM cell.
摘要:
The present invention provides a semiconductor structure that includes a substrate having a crystal lattice; a first structure formed in a first region of the substrate, the first structure includes at least a heterostructure that generates a lattice stress in said crystal lattice in the first region; and a second structure surrounding the first structure for preventing lattice stress from propagating outward from the first region of the substrate. The present invention also provides various methods for forming the semiconductor structure as well as other like structures.
摘要:
The present invention relates to methods and apparatus for improving the stability of static random access memory (SRAM) cells by using boosted word lines. Specifically, a boosted word line voltage (Vdd′) is applied to the word line of a selected SRAM cell, while such a boosted word line voltage (Vdd′) is sufficiently higher than the power supply voltage (Vdd) of the SRAM cell so as to improve the cell stability to a desired level. Specifically, a specific boosted word line voltage is predetermined for each SRAM cell based on the specific cell configuration, by using a circuit simulation program, such as the BERKELEY-SPICE simulation program. A boost voltage generator is then used to apply the predetermined boosted word line voltage to the selected SRAM cell.
摘要:
An ESD protection network is described which prevents high voltage oxide stress. The network consists of a filter network (such as a blocking capacitor) and diode protection elements. The filter network can be designed for several types of ESD protection functions. It can be designed to provide voltage reduction for ESD pulses, and to selectively block the frequency components of ESD pulses.
摘要:
A system and method for developing condensed netlists for sub-circuits within an integrated circuit and for modeling the performance of the integrated circuit based on the condensed netlists rather than full netlists. An IC layout is segmented into a plurality of sub-circuits, each comprising a group of one or more of a given type of active devices connected to (i.e., sharing) the same electrical sub-circuit terminals through a similar resistive network (i.e. such that they are subjected to approximately the same overall combined parasitic resistances). Full netlists corresponding to the sub-circuits are extracted from the layout and condensed. Each condensed netlist accounts for performance variations (e.g., as a function of variations in operating power supply voltages, operating temperatures and, optionally, self-heating and/or stress) exhibited by the active devices and resistive network in a sub-circuit. The condensed netlists for the sub-circuits are then simulated over the full range of operating temperatures and full range of operating power supply voltages for the integrated circuit in order to generate a performance model for the integrated circuit.
摘要:
A method (and computer program) identify shapes and locations of transistor elements within a geometric circuit layout. The transistor elements include an active area, at least one gate conductor and other transistor elements. Also, the gate conductor has sides running in a first direction, and has a width dimension running in a second direction perpendicular to the first direction. The method defines regions within the geometric circuit layout. To do so, the method defines a first region having a perimeter positioned along the sides of the gate conductor where the gate conductor intersects the active area and then expands the perimeter of the first region in the second direction to edges of the active area to define a perimeter of a second region. The first region and the second share perimeters in the first direction. The method then expands the perimeter of the second region in the first direction to define a perimeter of a third region. The second region and the third region share perimeters in the second direction. The method then separately evaluates effects the other transistor elements have within each of the first region, the second region, and the third region, to determine a characteristic of the gate conductor.
摘要:
The present invention relates to methods and apparatus for improving the stability of static random access memory (SRAM) cells by using boosted word lines. Specifically, a boosted word line voltage (Vdd′) is applied to the word line of a selected SRAM cell, while such a boosted word line voltage (Vdd′) is sufficiently higher than the power supply voltage (Vdd) of the SRAM cell so as to improve the cell stability to a desired level. Specifically, a specific boosted word line voltage is predetermined for each SRAM cell based on the specific cell configuration, by using a circuit simulation program, such as the BERKELEY-SPICE simulation program. A boost voltage generator is then used to apply the predetermined boosted word line voltage to the selected SRAM cell.
摘要:
A method of improving a circuit design for a very large scale integrated circuit is provided which represents a plurality of semiconductor devices interconnected in a circuit. It is determined whether an edge of a feature of one of the plurality of semiconductor devices in the design can be moved in a first direction by a distance within a permitted range, such that a performance goal and a matching goal for the circuit are served. If so, the edge is moved in the first direction by the distance calculated to best serve the performance goal and the matching goal. The foregoing steps may be repeated for each of the plurality of semiconductor devices. If necessary, the foregoing steps may be repeated until the performance goal and matching goal for the circuit are deemed to be adequately served.
摘要:
A computational methodology that improves the accuracy of model parameters in a compact model uses methods and algorithms to self-consistently match independently developed base and stress models by re-fitting the stress model to the data set that generates the base model. The re-fitting algorithm removes any discrepancy between the base model and the stress model as the stress model is applied to the data set obtained from a dimension-scaling macro. Stress offsets for dimension-scaling macro devices are calculated to fit the measured values of the model parameters for the same devices. The process of fitting the model parameters to the data set from the dimension-scaling macro calculates constant, linear, and quadratic coefficients for the model parameters, which are employed to increase the accuracy of the model parameters and of the compact model used in circuit simulations and optimization.
摘要:
A computational methodology that improves the accuracy of model parameters in a compact model uses methods and algorithms to self-consistently match independently developed base and stress models by re-fitting the stress model to the data set that generates the base model. The re-fitting algorithm removes any discrepancy between the base model and the stress model as the stress model is applied to the data set obtained from a dimension-scaling macro. Stress offsets for dimension-scaling macro devices are calculated to fit the measured values of the model parameters for the same devices. The process of fitting the model parameters to the data set from the dimension-scaling macro calculates constant, linear, and quadratic coefficients for the model parameters, which are employed to increase the accuracy of the model parameters and of the compact model used in circuit simulations and optimization.