公开(公告)号：US07302511B2

公开(公告)日：2007-11-27

申请号：US11251282

申请日：2005-10-13

申请人： Stalinselvaraj Jeyasingh ,  Andrew V. Anderson ,  Steven M. Bennett ,  Erik Cota-Robles ,  Alain Kagi ,  Gilbert Neiger ,  Richard Uhlig

发明人： Stalinselvaraj Jeyasingh ,  Andrew V. Anderson ,  Steven M. Bennett ,  Erik Cota-Robles ,  Alain Kagi ,  Gilbert Neiger ,  Richard Uhlig

IPC分类号： G06F13/24 ,  G06F13/26 ,  G06F9/445 ,  G06F12/00

CPC分类号： G06F13/24 ,  G06F9/45533 ,  G06F9/4812

摘要： In one embodiment, an apparatus includes a set of multiplex blocks coupled with an interrupt controller and multiple interrupt request lines, and a virtual machine monitor block (VMM) coupled to the set of multiplex blocks. Each multiplex block corresponds to a distinct interrupt request line. Each multiplex block is to route the interrupt request signal received via the corresponding interrupt request line either to the interrupt controller or the VMM block depending on a current configuration value of this multiplex block.

公开(公告)号：US07287197B2

公开(公告)日：2007-10-23

申请号：US10663205

申请日：2003-09-15

申请人： Steven M. Bennett ,  Andrew V. Anderson ,  Stalinselvaraj Jeyasingh ,  Alain Kagi ,  Gilbert Neiger ,  Richard Uhlig ,  Michael Kozuch ,  Lawrence Smith ,  Scott Rodgers

发明人： Steven M. Bennett ,  Andrew V. Anderson ,  Stalinselvaraj Jeyasingh ,  Alain Kagi ,  Gilbert Neiger ,  Richard Uhlig ,  Michael Kozuch ,  Lawrence Smith ,  Scott Rodgers

IPC分类号： G06F11/00

CPC分类号： G06F9/45533

摘要： In one embodiment, a request to transition control to a virtual machine (VM) is received from a virtual machine monitor (VMM) and a determination is made as to whether the VMM has requested a delivery of a fault to the VM. If the determination is positive, the fault is delivered to the VM when control is transitioned to the VM.

摘要翻译： 在一个实施例中，从虚拟机监视器（VMM）接收到转换到虚拟机（VM）的控制的请求，并且确定VMM是否已请求向VM发送故障。 如果确定为肯定，则当控制转换到VM时，将故障传递给VM。

公开(公告)号：US07177967B2

公开(公告)日：2007-02-13

申请号：US10676890

申请日：2003-09-30

申请人： Stalinselvaraj Jeyasingh ,  Andrew V. Anderson ,  Steven M. Bennett ,  Erik Cota-Robles ,  Alain Kagi ,  Gilbert Neiger ,  Richard Uhlig

发明人： Stalinselvaraj Jeyasingh ,  Andrew V. Anderson ,  Steven M. Bennett ,  Erik Cota-Robles ,  Alain Kagi ,  Gilbert Neiger ,  Richard Uhlig

IPC分类号： G06F13/24 ,  G06F13/26 ,  G06F9/445 ,  G06F12/00

CPC分类号： G06F13/24 ,  G06F9/45533 ,  G06F9/4812

摘要： In one embodiment, an apparatus includes a set of multiplex blocks coupled with an interrupt controller and multiple interrupt request lines, and a virtual machine monitor block (VMM) coupled to the set of multiplex blocks. Each multiplex block corresponds to a distinct interrupt request line. Each multiplex block is to route the interrupt request signal received via the corresponding interrupt request line either to the interrupt controller or the VMM block depending on a current configuration value of this multiplex block.

摘要翻译： 在一个实施例中，装置包括与中断控制器和多个中断请求线耦合的一组多路复用块以及耦合到该多路复用块集合的虚拟机监视块（VMM）。 每个复用块对应于不同的中断请求行。 每个多路复用块将根据该多路复用块的当前配置值将经由相应的中断请求线接收到的中断请求信号发送到中断控制器或VMM块。

公开(公告)号：US20120117300A1

公开(公告)日：2012-05-10

申请号：US12959109

申请日：2010-12-02

申请人： Erik C. Cota-Robles ,  Andy Glew ,  Stalinselvaraj Jeyasingh ,  Alain Kagi ,  Michael A. Kozuch ,  Gilbert Neiger ,  Richard Uhlig

发明人： Erik C. Cota-Robles ,  Andy Glew ,  Stalinselvaraj Jeyasingh ,  Alain Kagi ,  Michael A. Kozuch ,  Gilbert Neiger ,  Richard Uhlig

IPC分类号： G06F12/08

CPC分类号： G06F12/1027 ,  G06F9/30076 ,  G06F12/1036 ,  G06F2212/151

摘要： One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to a processor mode when an invalidation operation is performed. The processor mode is one of execution in a virtual machine (VM) and execution not in a virtual machine. The invalidation operation belongs to a non-empty set of invalidation operations composed of a union of (1) a possibly empty set of operations that invalidate a variable number of TLB entries, (2) a possibly empty set of operations that invalidate exactly one TLB entry, (3) a possibly empty set of operations that invalidate the plurality of TLB entries, (4) a possibly empty set of operations that enable and disable use of virtual memory, and (5) a possibly empty set of operations that configure physical address size, page size or other virtual memory system behavior in a manner that changes the manner in which a physical machine interprets the TLB entries.

摘要翻译： 本发明的一个实施例是使翻译后备缓冲器（TLB）中的条目无效的技术。 处理器中的TLB具有多个TLB条目。 当执行无效操作时，每个TLB条目与虚拟机扩展（VMX）标签字相关联，指示相关联的TLB条目是否根据处理器模式而无效。 处理器模式是虚拟机（VM）中的执行之一，而不是虚拟机中的执行。 无效操作属于一个无效的无效操作集合，它由（1）可能为空的操作集合组合，使一组可变数量的TLB条目无效，（2）一组可能的空白操作，使一个TLB无效 条目，（3）使多个TLB条目无效的可能的一组操作，（4）启用和禁用虚拟存储器的使用的可能的一组可能的空操作，以及（5）配置物理的可能的一组操作 地址大小，页面大小或其他虚拟内存系统行为，以改变物理机器解释TLB条目的方式。

公开(公告)号：US07318141B2

公开(公告)日：2008-01-08

申请号：US10322003

申请日：2002-12-17

申请人： Steve M. Bennett ,  Gilbert Neiger ,  Erik C. Cota-Robles ,  Stalinselvaraj Jeyasingh ,  Alain Kagi ,  Michael A. Kozuch ,  Richard A. Uhlig ,  Larry Smith ,  Dion Rodgers ,  Andrew Glew ,  Erich Boleyn

发明人： Steve M. Bennett ,  Gilbert Neiger ,  Erik C. Cota-Robles ,  Stalinselvaraj Jeyasingh ,  Alain Kagi ,  Michael A. Kozuch ,  Richard A. Uhlig ,  Larry Smith ,  Dion Rodgers ,  Andrew Glew ,  Erich Boleyn

IPC分类号： G06F12/06

CPC分类号： G06F9/45558 ,  G06F2009/45591

摘要： Methods and systems are provided to control the execution of a virtual machine (VM). A VM Monitor (VMM) accesses VM Control Structures (VMCS) indirectly through access instructions passed to a processor. In one embodiment, the access instructions include VMCS component identifiers used by the processor to determine the appropriate storage location for the VMCS components. The processor identifies the appropriate storage location for the VMCS component within the processor storage or within memory.

摘要翻译： 提供了方法和系统来控制虚拟机（VM）的执行。 VM监视器（VMM）通过传递给处理器的访问指令间接访问VM控制结构（VMCS）。 在一个实施例中，访问指令包括由处理器用于确定VMCS组件的适当存储位置的VMCS组件标识符。 处理器识别处理器存储器或存储器内的VMCS组件的适当存储位置。

公开(公告)号：US07296267B2

公开(公告)日：2007-11-13

申请号：US10194822

申请日：2002-07-12

申请人： Erik C. Cota-Robles ,  Randolph L. Campbell ,  Clifford D. Hall ,  Gilbert Neiger ,  Richard A. Uhlig

发明人： Erik C. Cota-Robles ,  Randolph L. Campbell ,  Clifford D. Hall ,  Gilbert Neiger ,  Richard A. Uhlig

IPC分类号： G06F9/455 ,  G06F9/46

CPC分类号： G06F9/505 ,  G06F9/45533 ,  G06F9/5044

摘要： System and method for binding virtual machines to hardware contexts. A method includes obtaining resource requirements for a plurality of virtual machines, and binding one or more of the plurality of virtual machines to one or more of a plurality of hardware contexts associated with a processor based upon the resource requirements. The resource requirements may be the bandwidth and latency of the virtual machines. The method may be implemented as software on a storage device on a computing device having a processor that supports multiple hardware contexts. The method is particularly beneficial for real-time virtual machines.

摘要翻译： 将虚拟机绑定到硬件上下文的系统和方法。 一种方法包括获得多个虚拟机的资源需求，并且基于资源需求，将多个虚拟机中的一个或多个绑定到与处理器相关联的多个硬件上下文中的一个或多个。 资源需求可能是虚拟机的带宽和延迟。 该方法可以被实现为具有支持多个硬件上下文的处理器的计算设备上的存储设备上的软件。 该方法对于实时虚拟机特别有益。

公开(公告)号：US07865670B2

公开(公告)日：2011-01-04

申请号：US10973678

申请日：2004-10-25

申请人： Erik C. Cota-Robles ,  Stalinselvaraj Jeyasingh ,  Alain Kagi ,  Michael A. Kozuch ,  Gilbert Neiger ,  Richard Uhlig

发明人： Erik C. Cota-Robles ,  Stalinselvaraj Jeyasingh ,  Alain Kagi ,  Michael A. Kozuch ,  Gilbert Neiger ,  Richard Uhlig

IPC分类号： G06F13/00

CPC分类号： G06F12/1027 ,  G06F9/30076 ,  G06F12/1036 ,  G06F2212/151

摘要： One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to a processor mode when an invalidation operation is performed. The processor mode is one of execution in a virtual machine (VM) and execution not in a virtual machine. The invalidation operation belongs to a non-empty set of invalidation operations composed of a union of (1) a possibly empty set of operations that invalidate a variable number of TLB entries, (2) a possibly empty set of operations that invalidate exactly one TLB entry, (3) a possibly empty set of operations that invalidate the plurality of TLB entries, (4) a possibly empty set of operations that enable and disable use of virtual memory, and (5) a possibly empty set of operations that configure physical address size, page size or other virtual memory system behavior in a manner that changes the manner in which a physical machine interprets the TLB entries.

摘要翻译： 本发明的一个实施例是使翻译后备缓冲器（TLB）中的条目无效的技术。 处理器中的TLB具有多个TLB条目。 当执行无效操作时，每个TLB条目与虚拟机扩展（VMX）标签字相关联，指示相关联的TLB条目是否根据处理器模式而无效。 处理器模式是虚拟机（VM）中的执行之一，而不是虚拟机中的执行。 无效操作属于一个无效的无效操作集合，它由（1）可能为空的操作集合组合，使一组可变数量的TLB条目无效，（2）一组可能的空白操作，使一个TLB无效 条目，（3）使多个TLB条目无效的可能的一组操作，（4）启用和禁用虚拟存储器的使用的可能的一组可能的空操作，以及（5）配置物理的可能的一组操作 地址大小，页面大小或其他虚拟内存系统行为，以改变物理机器解释TLB条目的方式。

公开(公告)号：US07127548B2

公开(公告)日：2006-10-24

申请号：US10124641

申请日：2002-04-16

申请人： Steve Bennett ,  Andrew V. Anderson ,  Erik Cota-Robles ,  Stalinselvaraj Jeyasingh ,  Alain Kagi ,  Gilbert Neiger ,  Richard Uhlig ,  Michael A. Kozuch

发明人： Steve Bennett ,  Andrew V. Anderson ,  Erik Cota-Robles ,  Stalinselvaraj Jeyasingh ,  Alain Kagi ,  Gilbert Neiger ,  Richard Uhlig ,  Michael A. Kozuch

IPC分类号： G06F12/00

CPC分类号： G06F9/45533 ,  G06F9/468

摘要： In one embodiment, a command pertaining to one or more portions of a register is received from guest software. Further, a determination is made as to whether the guest software has access to all of the requested portions of the register based on indicators within a mask field that correspond to the requested portions of the register. If the guest software has access to all of the requested portions of the register, the command received from the guest software is executed on the requested portions of the register.

公开(公告)号：US06996748B2

公开(公告)日：2006-02-07

申请号：US10184798

申请日：2002-06-29

申请人： Richard Uhlig ,  Andrew V. Anderson ,  Steve Bennett ,  Erik Cota-Robles ,  Stalinselvaraj Jeyasingh ,  Alain Kagi ,  Gilbert Neiger

发明人： Richard Uhlig ,  Andrew V. Anderson ,  Steve Bennett ,  Erik Cota-Robles ,  Stalinselvaraj Jeyasingh ,  Alain Kagi ,  Gilbert Neiger

IPC分类号： G06F11/00

CPC分类号： G06F11/0712 ,  G06F11/0751

摘要： In one embodiment, fault information relating to a fault associated with the operation of guest software is received. Further, a determination is made as to whether the fault information satisfies one or more fault filtering criteria. If the determination is positive, the guest software is permitted to disregard the fault.

摘要翻译： 在一个实施例中，接收到与客户软件的操作相关联的故障的故障信息。 此外，确定故障信息是否满足一个或多个故障过滤标准。 如果确定是肯定的，则客户软件被允许忽略该故障。

公开(公告)号：US10515023B2

公开(公告)日：2019-12-24

申请号：US15088739

申请日：2016-04-01

申请人： Ravi L. Sahita ,  Gilbert Neiger ,  Vedvyas Shanbhogue ,  David M. Durham ,  Andrew V. Anderson ,  David A. Koufaty ,  Asit K. Mallick ,  Arumugam Thiyagarajah ,  Barry E. Huntley ,  Deepak K. Gupta ,  Michael Lemay ,  Joseph F. Cihula ,  Baiju V. Patel

发明人： Ravi L. Sahita ,  Gilbert Neiger ,  Vedvyas Shanbhogue ,  David M. Durham ,  Andrew V. Anderson ,  David A. Koufaty ,  Asit K. Mallick ,  Arumugam Thiyagarajah ,  Barry E. Huntley ,  Deepak K. Gupta ,  Michael Lemay ,  Joseph F. Cihula ,  Baiju V. Patel

IPC分类号： G06F12/00 ,  G06F12/14 ,  G06F12/1009 ,  G06F9/455 ,  G06F12/1027 ,  G06F21/78

摘要： This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.