公开(公告)号：US20110183636A1

公开(公告)日：2011-07-28

申请号：US12692214

申请日：2010-01-22

申请人： Joseph Staudinger ,  John M. Pigott ,  Eric J. Toulouse

发明人： Joseph Staudinger ,  John M. Pigott ,  Eric J. Toulouse

IPC分类号： H04B1/02 ,  H03F3/16 ,  H03C1/00

CPC分类号： H04B1/0475 ,  H03C1/36 ,  H03F1/0222 ,  H03F1/0288 ,  H03F3/193 ,  H03F3/245 ,  H03F3/604 ,  H03F2200/18 ,  H03F2200/255 ,  H03F2200/315 ,  H03F2200/336 ,  H03F2200/423 ,  H03F2200/451 ,  H03F2200/543

摘要： A circuit including a carrier amplifier having an input, an output, a first transistor coupled to a first power supply voltage terminal for receiving a modulated power supply voltage, and a second transistor coupled to a second power supply voltage terminal for receiving a fixed power supply voltage is provided. The circuit further includes a peaking amplifier having an input coupled to the input of the carrier amplifier and an output coupled to the output of the carrier amplifier.

摘要翻译： 一种电路，包括具有输入端，输出端，耦合到第一电源电压端子的第一晶体管用于接收调制电源电压的载波放大器，以及耦合到第二电源电压端子的第二晶体管，用于接收固定电源 提供电压。 该电路还包括峰值放大器，其具有耦合到载波放大器的输入的输入端和耦合到载波放大器的输出的输出。

公开(公告)号：US20100271078A1

公开(公告)日：2010-10-28

申请号：US12429491

申请日：2009-04-24

申请人： Ira G. Miller ,  John M. Pigott

发明人： Ira G. Miller ,  John M. Pigott

IPC分类号： H03K3/00 ,  H03L5/00

CPC分类号： H03K3/356113 ,  H02M1/08 ,  H02M3/1588 ,  H03K3/0375 ,  H03K17/6874 ,  H03K2217/0081 ,  Y02B70/1466

摘要： A driver circuit includes a first and a second voltage rail, a first pre-driver circuit, a power transistor, comparison circuitry which indicates when a voltage level of the first voltage rails is above or below a reference voltage level, a level shift circuit coupled between the first voltage rail and the second voltage rail which provides a level shifted output, a tapered buffer circuit coupled to the first voltage rail and to a first circuit node, wherein the tapered buffer circuit receives the level shifted output and provides a buffered output to a control electrode of the first pre-driver transistor, and a rail voltage adjusting circuit coupled between the first circuit node and the second voltage rail, which, in response to the comparison circuitry indicating that the voltage level of the first voltage rail is above the reference voltage level, adjusts a voltage level of the second voltage rail.

摘要翻译： 驱动器电路包括第一和第二电压轨，第一预驱动器电路，功率晶体管，比较电路，其指示第一电压轨的电压电平何时高于或低于参考电压电平;电平移位电路耦合 在提供电平移位输出的第一电压轨和第二电压轨之间，耦合到第一电压轨和第一电路节点的渐缩缓冲电路，其中锥形缓冲电路接收电平移位输出并提供缓冲输出 所述第一预驱动晶体管的控制电极以及耦合在所述第一电路节点和所述第二电压轨之间的轨电压调整电路，所述轨电压调整电路响应于所述比较电路，指示所述第一电压轨的电压高于 参考电压电平，调整第二电压轨的电压电平。

公开(公告)号：US07808286B1

公开(公告)日：2010-10-05

申请号：US12429491

申请日：2009-04-24

申请人： Ira G. Miller ,  John M. Pigott

发明人： Ira G. Miller ,  John M. Pigott

IPC分类号： H03K3/00

CPC分类号： H03K3/356113 ,  H02M1/08 ,  H02M3/1588 ,  H03K3/0375 ,  H03K17/6874 ,  H03K2217/0081 ,  Y02B70/1466

摘要： A driver circuit includes a first and a second voltage rail, a first pre-driver circuit, a power transistor, comparison circuitry which indicates when a voltage level of the first voltage rails is above or below a reference voltage level, a level shift circuit coupled between the first voltage rail and the second voltage rail which provides a level shifted output, a tapered buffer circuit coupled to the first voltage rail and to a first circuit node, wherein the tapered buffer circuit receives the level shifted output and provides a buffered output to a control electrode of the first pre-driver transistor, and a rail voltage adjusting circuit coupled between the first circuit node and the second voltage rail, which, in response to the comparison circuitry indicating that the voltage level of the first voltage rail is above the reference voltage level, adjusts a voltage level of the second voltage rail.

摘要翻译： 驱动器电路包括第一和第二电压轨，第一预驱动器电路，功率晶体管，比较电路，其指示第一电压轨的电压电平何时高于或低于参考电压电平;电平移位电路耦合 在提供电平移位输出的第一电压轨和第二电压轨之间，耦合到第一电压轨和第一电路节点的渐缩缓冲电路，其中锥形缓冲电路接收电平移位输出并提供缓冲输出 所述第一预驱动晶体管的控制电极以及耦合在所述第一电路节点和所述第二电压轨之间的轨电压调整电路，所述轨电压调整电路响应于所述比较电路，指示所述第一电压轨的电压高于 参考电压电平，调整第二电压轨的电压电平。

公开(公告)号：US07800350B2

公开(公告)日：2010-09-21

申请号：US11747360

申请日：2007-05-11

申请人： John M. Pigott

发明人： John M. Pigott

IPC分类号： G05F1/40

CPC分类号： H02M3/1588 ,  H02M1/38 ,  Y02B70/1466

摘要： Deadtime optimization techniques and circuits are provided which implement closed loop feedback to reduce a duration of a deadtime interval by reducing a diode conduction time (DCT) to an optimized or minimized value. Information regarding DCT is fed back to continuously adjust the relative delay between a first driver path which drives a first transistor and a second driver path which drives a second transistor. For instance, information regarding DCT can be measured and stored, and then used to generate a control signal which continuously adjusts (e.g., increases or decreases) a variable delay associated with a delay element in one of the driver paths of one of the transistors. The delay is adjusted to a value which drives the DCT towards an optimum value. By continuously changing the relative delay between the first driver path and the second driver path, the DCT can be driven to an optimum value.

摘要翻译： 提供了死区优化技术和电路，其实现闭环反馈以通过将二极管导通时间（DCT）减小到优化或最小化的值来减少死区间隔的持续时间。 反馈关于DCT的信息，以连续地调节驱动第一晶体管的第一驱动路径和驱动第二晶体管的第二驱动路径之间的相对延迟。 例如，可以测量和存储关于DCT的信息，然后用于产生一个控制信号，该控制信号连续调整（例如，增加或减少）与其中一个晶体管之一的驱动器路径中的延迟元件相关联的可变延迟。 将延迟调整为将DCT驱动到最佳值的值。 通过连续地改变第一驱动路径和第二驱动路径之间的相对延迟，可以将DCT驱动到最佳值。

公开(公告)号：US20090251117A1

公开(公告)日：2009-10-08

申请号：US12098883

申请日：2008-04-07

申请人： John M. Pigott

发明人： John M. Pigott

IPC分类号： G05F1/00

CPC分类号： H02M3/1584

摘要： A power converter (10) includes a controller (12) configured to generate a switching signal. A first section (14) is coupled to the controller (12) and has first and second switches (26,30). The first section (14) is configured such that the first and second switches (26,30) operate in an alternating manner in response to the switching signal. A second section (16) is coupled to the controller (12) and has third and fourth switches (50,54). The second section (16) is configured such that the third and fourth switches (50,54) operate in an alternating manner in response to the switching signal. The first and second sections (14,16) are coupled to a node (88). A detection circuit (18) is coupled to the second section (16). The detection circuit (18) is configured to measure a voltage at the node between the operation of the third and fourth switches (50,54) and deactivate the second section when the voltage is above a predetermined threshold.

摘要翻译： 电力转换器（10）包括被配置为产生开关信号的控制器（12）。 第一部分（14）耦合到控制器（12）并具有第一和第二开关（26,30）。 第一部分（14）被配置为使得第一和第二开关（26,30）响应于切换信号以交替方式操作。 第二部分（16）耦合到控制器（12）并且具有第三和第四开关（50,54）。 第二部分（16）被配置为使得第三和第四开关（50,54）响应于切换信号以交替方式操作。 第一和第二部分（14,16）耦合到节点（88）。 检测电路（18）耦合到第二部分（16）。 检测电路（18）被配置为测量在第三和第四开关（50,54）的操作之间的节点处的电压，并且当电压高于预定阈值时，去激活第二部分。

公开(公告)号：US07439787B2

公开(公告)日：2008-10-21

申请号：US11495265

申请日：2006-07-27

申请人： Ahmed E. Hashim ,  John M. Pigott

发明人： Ahmed E. Hashim ,  John M. Pigott

IPC分类号： H03K3/017

CPC分类号： H03L7/0812 ,  H03L7/07 ,  H03L7/0805

摘要： A pulse width modulation circuit includes a first delay-locked loop (DLL) circuit and a second DLL circuit. The first DLL is coupled to a first multiplexer and has a first set of delay stages, wherein the first DLL circuit is configured to receive an input clock signal and, through the first multiplexer, produce a first stage delay signal associated with the first set of delay stages, wherein the first stage delay signal leads the input clock signal by a first duration. The second DLL circuit is coupled to a second multiplexer and has a second set of delay stages, wherein the second DLL circuit is configured to receive the input clock signal and, through the second multiplexer, produce a second stage delay signal associated with the second set of delay stages, wherein the second stage delay signal lags the first stage delay signal by a second duration; wherein the first DLL circuit and second DLL circuit are operatively coupled to produce an output signal having a pulse width equal to the difference between the first duration and the second duration.

摘要翻译： 脉宽调制电路包括第一延迟锁定环（DLL）电路和第二DLL电路。 第一DLL耦合到第一多路复用器并且具有第一组延迟级，其中第一DLL电路被配置为接收输入时钟信号，并且通过第一多路复用器产生与第一组延迟相关联的第一级延迟信号 延迟级，其中第一级延迟信号将输入时钟信号引导第一持续时间。 第二DLL电路耦合到第二多路复用器并且具有第二组延迟级，其中第二DLL电路被配置为接收输入时钟信号，并且通过第二多路复用器产生与第二组相关联的第二级延迟信号 的延迟级，其中第二级延迟信号延迟第一级延迟信号第二持续时间; 其中所述第一DLL电路和所述第二DLL电路被可操作地耦合以产生具有等于所述第一持续时间和所述第二持续时间之间的差的脉冲宽度的输出信号。

公开(公告)号：US06166653A

公开(公告)日：2000-12-26

申请号：US133226

申请日：1998-08-13

申请人： Peter Hans Schulmeyer ,  Joachim Kruecken ,  John M. Pigott

发明人： Peter Hans Schulmeyer ,  Joachim Kruecken ,  John M. Pigott

IPC分类号： G06F13/14 ,  B60R21/01 ,  B60R21/16 ,  G05B19/042 ,  G06F15/177 ,  H04L12/403 ,  H04Q5/22

CPC分类号： H04L12/10 ,  G05B19/042 ,  G05B2219/21028 ,  G05B2219/25232 ,  H04L12/403 ,  H04L2012/40273

摘要： A method and apparatus for assigning unique addresses to each generic "node" in a distributed control system that contains a main controller (52) coupled to a plurality of generic nodes (54) via a distributed communication bus (55). The main controller (52) provides currents and/or voltages to the communication bus (55) via a supply (58). In one embodiment, each node (54) processes the current and voltages to store reference voltages and distance voltages proportional to its distance along the communication bus (55). In another embodiment, each node (54) signals to the main controller (52) when the distance voltage reaches a certain value relative to the reference voltage. The main controller (52) processes the arrival times of these signals to determine a relative distance to each node (54). This distance information is used to assign a unique address to each generic node (54) for identification during normal mode of operation.

公开(公告)号：US6166451A

公开(公告)日：2000-12-26

申请号：US232253

申请日：1999-01-14

申请人： John M. Pigott

发明人： John M. Pigott

IPC分类号： B60R21/01 ,  H02H11/00 ,  H02H3/20

CPC分类号： B60R21/017 ,  B60R2021/01068 ,  B60R2021/01075 ,  H02H11/002 ,  Y10S320/15 ,  Y10T307/839 ,  Y10T307/931

摘要： A distributed airbag firing system (10) includes a controller (12) receiving sensor signals from a sensor (20) over a two-wire bus (18). The controller provides a firing command over to the two-wire bus to a squib driver circuit (26), which provides the firing current necessary to detonate a squib device (32) and inflate the airbag. The squib driver circuit includes a rectifier (42) with its first and second inputs interchangeably connected to the two-wire bus. The rectifier circuit converts the voltage orientation on the first and second conductors to a positive potential on a first output conductor and a negative or ground potential on a second output conductor. The interchangeability of the first and second inputs of the rectifier to the two-wire bus makes the connection arbitrary and fail-safe.

摘要翻译： 分布式气囊燃烧系统（10）包括控制器（12），其通过双线总线（18）接收来自传感器（20）的传感器信号。 所述控制器向所述二线总线提供对点火驱动器电路（26）的触发命令，所述点火驱动器电路（26）提供引爆所述爆管装置（32）并使所述气囊膨胀所需的点火电流。 爆管驱动器电路包括整流器（42），其第一和第二输入可互换地连接到双线总线。 整流电路将第一和第二导体上的电压取向转换为第一输出导体上的正电位和第二输出导体上的负电位或接地电位。 整流器的第一和第二输入与双线总线的互换性使得连接任意且故障安全。

公开(公告)号：US6069493A

公开(公告)日：2000-05-30

申请号：US980250

申请日：1997-11-28

申请人： John M. Pigott ,  Stephan Ollitrault ,  Damon Peter Broderick

发明人： John M. Pigott ,  Stephan Ollitrault ,  Damon Peter Broderick

IPC分类号： H01L27/02 ,  H03K19/003 ,  H03K19/0175 ,  H03K17/16

CPC分类号： H01L27/0266 ,  H01L27/0255 ,  H03K19/00315

摘要： An input circuit (20) and a method for protecting the input circuit (20) from positive and negative overvoltages. The input circuit (20) includes an N-channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) (12), a P-channel MOSFET (13), a Zener diode (21), and a diode-connected transistor (22). The P-channel MOSFET (13) protects the N-channel MOSFET (12) from negative overvoltages. The Zener diode (21) and the diode-connected transistor (22) protect the N-channel MOSFET (12) from positive overvoltages. In addition, the Zener diode (21) protects the P-channel MOSFET (13) from positive overvoltages.

摘要翻译： 输入电路（20）和用于保护输入电路（20）不受正和负过电压的方法。 输入电路（20）包括N沟道金属氧化物半导体场效应晶体管（MOSFET）（12），P沟道MOSFET（13），齐纳二极管（21）和二极管连接晶体管（22）。 P沟道MOSFET（13）保护N沟道MOSFET（12）免于负的过电压。 齐纳二极管（21）和二极管连接晶体管（22）保护N沟道MOSFET（12）免于正过电压。 此外，齐纳二极管（21）保护P沟道MOSFET（13）免于正过电压。

公开(公告)号：US5111381A

公开(公告)日：1992-05-05

申请号：US743955

申请日：1991-08-12

申请人： John M. Pigott ,  Robert B. Jarrett

发明人： John M. Pigott ,  Robert B. Jarrett

IPC分类号： H02M7/219 ,  H02M7/5387 ,  H02P7/00 ,  H03K17/687

CPC分类号： H02M7/5387 ,  H02P7/04 ,  H02M2003/1555

摘要： A circuit for discharging an inductive load of an H-bridge circuit at a controlled rate has been provided. When a first half of the H-bridge circuit is switched from a conductive state to a non-conductive state, the circuit clamps a first side of the inductive load, while creating a recirculation path to discharge the inductive load at a controlled rate.A similar circuit may be utilized when a second (complementary) half of the H-bridge circuit is switched from a conductive state to a non-conductive state wherein the similar circuit clamps a second side of the inductive load, while creating a recirculation path to discharge the inductive load at a controlled rate.

摘要翻译： 已经提供了用于以受控速率放电H桥电路的感性负载的电路。 当H桥电路的前半部分从导通状态切换到非导通状态时，电路夹着感性负载的第一侧，同时产生再循环路径以以受控的速率放电感性负载。 当H桥电路的第二（互补）一半从导通状态切换到非导通状态时，可以使用类似的电路，其中类似电路夹紧感应负载的第二侧，同时创建再循环路径 以受控的速率放电感性负载。