公开(公告)号：US10276442B1

公开(公告)日：2019-04-30

申请号：US15993017

申请日：2018-05-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Julien Frougier ,  Kangguo Cheng ,  Adra Carr ,  Nicolas Loubet

IPC: H01L29/76 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/786

Abstract: Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A first field-effect transistor has a first source/drain region, and a second field-effect transistor has a second source/drain region. A first silicide layer is arranged to wrap around the first source/drain region, and a second silicide layer is arranged to wrap around the second source/drain region. The first silicide layer contains a first metal, and the second silicide layer contains a second metal different from the first metal.

公开(公告)号：US10236218B1

公开(公告)日：2019-03-19

申请号：US15900264

申请日：2018-02-20

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Ruilong Xie ,  Julien Frougier ,  Hiroaki Niimi ,  Nigel Cave ,  Xusheng Kevin Wu

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3213

Abstract: At least one method, apparatus and system disclosed herein involves forming semiconductor devices comprising dual silicides in contacts to FinFETs. The semiconductor device may comprise a PFET fin; an NFET fin; a first metal silicide around the NFET fin; a second metal silicide around the PFET fin; and a fill metal around the second metal silicide, above the PFET fin, and above the NFET fin. Methods of forming such devices are also disclosed.

公开(公告)号：US20190074224A1

公开(公告)日：2019-03-07

申请号：US15695229

申请日：2017-09-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Julien Frougier ,  Min Gyu Sung ,  Edward Joseph Nowak ,  Nigel G. Cave ,  Lars Liebmann ,  Daniel Chanemougame ,  Andreas Knorr

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: The disclosure is directed to gate all-around integrated circuit structures, finFETs having a dielectric isolation, and methods of forming the same. The gate all-around integrated circuit structure may include a first insulator region within a substrate; a pair of remnant liner stubs disposed within the first insulator region; a second insulator region laterally adjacent to the first insulator region within the substrate; a pair of fins over the first insulator region, each fin in the pair of fins including an inner sidewall facing the inner sidewall of an adjacent fin in the pair of fins and an outer sidewall opposite the inner sidewall; and a gate structure substantially surrounding an axial portion of the pair of fins and at least partially disposed over the first and second insulator regions, wherein each remnant liner stub is substantially aligned with the inner sidewall of a respective fin of the pair of fins.