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公开(公告)号：US20170134038A1
公开(公告)日：2017-05-11
申请号：US15116095
申请日：2014-04-26
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan
CPC classification number: H03M1/808 , G11C2213/75 , H01L45/1253 , H01L45/145 , H03M1/78 , H03M1/785
Abstract: Switched memristor digital-to-analog conversion employs a set of switch-selectable programmed resistances corresponding to a digital-to-analog conversion mapping to convert a digital input into an analog output. The digital input is to establish an analog resistance of a plurality of switched memristors connected in series that are switch selectable. The plurality of switched memristors is to provide the set of switch-selectable programmed resistances in accordance with the digital-to-analog conversion mapping.
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公开(公告)号：US20170133088A1
公开(公告)日：2017-05-11
申请号：US15318000
申请日：2014-07-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C13/0002 , G11C13/0061 , G11C16/10 , G11C29/026 , G11C29/028 , G11C2013/0052 , G11C2213/15
Abstract: An example device in accordance with an aspect of the present disclosure includes a first module, a second module, and a third module. The first module is coupled to an element whose status is to be determined, and the first module is to receive an input current that increases over time. The second module is to perform a temporal derivative of a voltage across the element. The third module is to provide an output signal based on a current behavior of the element, according to a change in voltage as a function of a change in current.
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公开(公告)号：US10706922B2
公开(公告)日：2020-07-07
申请号：US16063804
申请日：2016-01-26
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan , Le Zheng , John Paul Strachan
Abstract: In one example in accordance with the present disclosure a device is described. The device includes a cross-bar array of memristive elements. Each memristive element has a conductance value. The device also includes a column of offset elements. An offset element is coupled to a row of memristive elements and has a conductance value. The device also includes a number of accumulation elements. An accumulation element is coupled to a column of memristive elements. The accumulation element collects an intermediate output from the column and subtracts from the intermediate output an output from the column of offset elements.
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公开(公告)号：US20200026995A1
公开(公告)日：2020-01-23
申请号：US16037060
申请日：2018-07-17
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Brent Buchanan , John Paul Strachan , Le Zheng
Abstract: A circuit for a neuron of a multi-stage compute process is disclosed. The circuit comprises a weighted charge packet (WCP) generator. The circuit may also include a voltage divider controlled by a programmable resistance component (e.g., a memristor). The WCP generator may also include a current mirror controlled via the voltage divider and arrival of an input spike signal to the neuron. WCPs may be created to represent the multiply function of a multiply accumulate processor. The WCPs may be supplied to a capacitor to accumulate and represent the accumulate function. The value of the WCP may be controlled by the length of the spike in signal times the current supplied through the current mirror. Spikes may be asynchronous. Memristive components may be electrically isolated from input spike signals so their programmed conductance is not affected. Positive and negative spikes and WCPs for accumulation may be supported.
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公开(公告)号：US10424378B2
公开(公告)日：2019-09-24
申请号：US16073922
申请日：2016-02-24
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan , Le Zheng , John Paul Strachan
Abstract: In one example in accordance with the present disclosure a control circuit is described. The control circuit includes a source following component to receive an input voltage and output a switching voltage. The circuit also includes an input leg of a current mirror coupled to the source following component. The input leg of the current mirror replicates the switching voltage to an output leg of the current mirror of a memristive bit cell. The circuit also includes a number of current control components. At least one of the current control components enforces a constant current through the source following component and other current control components maintain the input leg of the current mirror and the output leg of the current mirror at the same current.
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Patent Agency Ranking
公开(公告)号：US10418810B2
公开(公告)日：2019-09-17
申请号：US15540192
申请日：2015-01-28
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan , Richard J. Auletta , Ning Ge
IPC: H02H9/04 , G11C13/00 , H01L27/02 , H01L45/00 , H01L27/092 , H01L21/8234 , G11C29/50
Abstract: In the examples provided herein, an electrostatic discharge (ESD) recording circuit has a first memristive element coupled to a pin of an integrated circuit. The first memristive element switches from a first resistance to a second resistance when an ESD event occurs at the pin, and the first resistance is less than the second resistance. The ESD recording circuit also has shunting circuitry to shunt energy from an additional ESD event away from the first memristive element.
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公开(公告)号：US10347352B2
公开(公告)日：2019-07-09
申请号：US15500568
申请日：2015-04-29
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan
Abstract: According to an example, discrete-time analog filtering may include receiving an input signal, and sampling the input signal to determine sampled input signal values related to the input signal.
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公开(公告)号：US20190108193A1
公开(公告)日：2019-04-11
申请号：US16213385
申请日：2018-12-07
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan
CPC classification number: G06F17/16 , G06F7/50 , G06F7/523 , G06F7/5443 , G06F2207/4802 , G11C7/1006 , G11C13/004 , G11C2213/77
Abstract: In one example in accordance with the present disclosure a resistive memory array is described. The array includes a number of resistive memory elements to receive a common-valued read signal. The array also includes a number of multiplication engines to perform a multiply operation by receiving a memory element output from a corresponding resistive memory element, receiving an input signal, and generating a multiplication output based on a received memory element output and a received input signal. The array also includes an accumulation engine to sum multiplication outputs from the number of multiplication engines.
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公开(公告)号：US20190027217A1
公开(公告)日：2019-01-24
申请号：US16065771
申请日：2016-01-27
Applicant: Hewlett Packard Enterprise Development LP
Inventor： John Paul Strachan , Brent Buchanan , Le Zheng
Abstract: In one example in accordance with the present disclosure a memristive array is described. The array includes a number of memristive devices. A memristive device is switchable between states and is to store information. The memristive array also includes a parallel reset control device coupled to the number of memristive devices in parallel. The parallel reset control device regulates a resetting operation for the number of memristive devices by regulating current flow through target memristive devices.
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公开(公告)号：US10090030B1
公开(公告)日：2018-10-02
申请号：US15581159
申请日：2017-04-28
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Ali Shafiee Ardestani , Naveen Muralimanohar , Brent Buchanan
Abstract: Examples disclosed herein relate to a circuit having first and second analog processors and an analog-to-digital converter coupled to the first and second analog processors. The first analog processor provides a first analog signal having a voltage representing a function of a first vector and a second vector. The second analog processor provides a second analog signal having a voltage representing a function of a binary inverse of the first vector and the second vector. The analog-to-digital converter receives the first analog signal and the second analog signal, compares a signal selected from a group consisting of the first analog signal and the second analog signal to a reference voltage and based on the comparison to the reference voltage, determines a digital result representing the function of the first vector and the second vector.
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