公开(公告)号：US5604700A

公开(公告)日：1997-02-18

申请号：US506989

申请日：1995-07-28

申请人： Patrice M. Parris ,  Yee-Chaung See

发明人： Patrice M. Parris ,  Yee-Chaung See

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C17/08 ,  H01L27/115 ,  G11C11/34

CPC分类号： H01L27/115

摘要： A non-volatile memory cell (10) is provided employing two transistors (11, 12) connected in series. A floating gate structure (13), formed with a single polysilicon deposition, is shared by each transistor (11, 12) to store the logic condition of the memory cell (10). To program and erase the memory cell (10), a voltage potential is placed on the floating gate (13) which modulates the transistors (11, 12) so only one is conducting during read operations. The gate capacitance of the transistors (11, 12) is used to direct the movement of electrons on or off the floating gate structure (13) to place or remove the stored voltage potential. The two transistor memory cell (10) couples one of two voltage potentials as the output voltage so no sense amp or buffer circuitry is required. The memory cell (10) can be constructed using traditional CMOS processing methods since no additional process steps or device elements are required.

摘要翻译： 使用串联连接的两个晶体管（11,12）来提供非易失性存储单元（10）。 形成有单个多晶硅沉积的浮栅结构（13）由每个晶体管（11,12）共享以存储存储单元（10）的逻辑条件。 为了对存储单元（10）进行编程和擦除，在浮动栅极（13）上放置一个电压电位，调制晶体管（11,12），因此只有一个在读取操作期间导通。 晶体管（11,12）的栅极电容用于引导电子在浮动栅极结构（13）上或离开浮动栅极结构（13）的移动，以放置或去除存储的电压电位。 两个晶体管存储单元（10）将两个电压电位之一耦合作为输出电压，因此不需要读出放大器或缓冲器电路。 可以使用传统的CMOS处理方法来构造存储单元（10），因为不需要额外的工艺步骤或器件元件。

公开(公告)号：US20110101465A1

公开(公告)日：2011-05-05

申请号：US13004396

申请日：2011-01-11

申请人： Moaniss Zitouni ,  Patrice M. Parris

发明人： Moaniss Zitouni ,  Patrice M. Parris

IPC分类号： H01L27/092

CPC分类号： H01L27/0921 ,  H01L21/823878

摘要： Latch-up of CMOS devices is improved by using a structure having electrically coupled but floating doped regions between the N-channel and P-channel devices. The doped regions desirably lie substantially parallel to the source-drain regions of the devices between the Pwell and Nwell regions in which the source-drain regions are located. A first (“N BAR”) doped region forms a PN junction with the Pwell, spaced apart from a source/drain region in the Pwell, and a second (“P BAR”) doped region forms a PN junction with the Nwell, spaced apart from a source/drain region in the Nwell. A further NP junction lies between the N BAR and P BAR regions. The N BAR and P BAR regions are ohmically coupled, preferably by a low resistance metal conductor, and otherwise floating with respect to the device or circuit reference potentials (e.g., Vss, Vdd).

摘要翻译： 通过使用在N沟道和P沟道器件之间具有电耦合但浮置的掺杂区域的结构来提高CMOS器件的锁存。 掺杂区域理想地基本上平行于源极 - 漏极区域所在的P阱和Nwell区域之间的器件的源极 - 漏极区域。 第一（“N BAR”）掺杂区域与P阱形成PN结，与P阱中的源/漏区间隔开，并且第二（“P BAR”）掺杂区域与Nwell形成PN结，间隔开 除了Nwell中的源/漏区外。 另外的NP连接点位于N BAR和P BAR区域之间。 N BAR和P BAR区域优选地通过低电阻金属导体欧姆耦合，否则相对于器件或电路参考电位（例如Vss，Vdd）浮置。

公开(公告)号：US07892907B2

公开(公告)日：2011-02-22

申请号：US12262922

申请日：2008-10-31

申请人： Moaniss Zitouni ,  Patrice M. Parris

发明人： Moaniss Zitouni ,  Patrice M. Parris

IPC分类号： H01L21/00

CPC分类号： H01L27/0921 ,  H01L21/823878

摘要： Latch-up of CMOS devices (20, 20′) is improved by using a structure (40, 40′, 80) having electrically coupled but floating doped regions (64, 64′; 65, 65′) between the N-channel (44) and P-channel (45) devices. The doped regions (64, 64′; 65, 65′) desirably lie substantially parallel to the source-drain regions (422, 423; 432, 433) of the devices (44, 45) between the Pwell (42) and Nwell (43) regions in which the source-drain regions (422, 423; 432, 433) are located. A first (“N BAR”) doped region (64, 64′) forms a PN junction (512) with the Pwell (42), spaced apart from a source/drain region (423) in the Pwell (42), and a second (“P BAR”) doped region (55, 55′) forms a PN junction (513) with the Nwell (43), spaced apart from a source/drain region (433) in the Nwell (43). A further NP junction (511) lies between the N BAR (64) and P BAR (65) regions. The N BAR (64) and P BAR (65) regions are ohmically coupled, preferably by a low resistance metal conductor (62), and otherwise floating with respect to the device or circuit reference potentials (e.g., Vss, Vdd).

摘要翻译： 通过使用具有电耦合但浮置的掺杂区域（64,64'; 65,65'）的结构（40,40'，80）来改善CMOS器件（20,20'）的锁存，N结构 44）和P沟道（45）器件。 掺杂区域（64,64'; 65,65'）理想地位于Pwell（42）和Nwell（...）之间的器件（44,45）的源极 - 漏极区域（422,423; 432,433） 43）源极 - 漏极区域（422,423,432,433）所在的区域。 第一（“N BAR”）掺杂区域（64,64'）与Pwell（42）中的P阱（42）形成PN结（512），与Pwell（42）中的源极/漏极区域（423）间隔开，并且 第二（“P BAR”）掺杂区域（55,55'）与N阱（43）中的源极/漏极区域（433）间隔开，形成具有N阱（43）的PN结（513）。 另外的NP结（511）位于N BAR（64）和P BAR（65）区之间。 N BAR（64）和P BAR（65）区域优选地通过低电阻金属导体（62）欧姆耦合，并且否则相对于器件或电路参考电位（例如，Vss，Vdd）浮置。

公开(公告)号：US5777361A

公开(公告)日：1998-07-07

申请号：US657127

申请日：1996-06-03

申请人： Patrice M. Parris ,  Yee-Chaung See

发明人： Patrice M. Parris ,  Yee-Chaung See

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC分类号： H01L29/7885

摘要： A nonvolatile memory cell (10) includes a single n-channel insulated gate FET (11) having a single floating gate (12). The FET (11) operates asymmetrically in a sense that the capacitance of a parasitic gate-source capacitor (24) is smaller than the capacitance of a parasitic gate-drain capacitor (26). The asymmetric condition is achievable either by fabricating the FET (11) as an asymmetric structure (30, 60) or by adjusting the capacitance of the parasitic capacitors (24, 26) through terminal biasing when the FET (11) is a short channel device. The potential of the floating gate (12) is controlled by biasing the source (14), drain (16), and substrate (18) of the FET (11). The cell (10) is programmed by moving charge onto the floating gate (12) via hot carrier injection, erased by moving charge from the floating gate (12) via tunneling, and read by sensing the conductive state of the FET (11).

摘要翻译： 非易失性存储单元（10）包括具有单个浮动栅极（12）的单个n沟道绝缘栅极FET（11）。 FET（11）在寄生栅 - 源电容器（24）的电容小于寄生栅 - 漏电容器（26）的电容的意义上不对称地工作。 通过将FET（11）制造为不对称结构（30,60）或者当FET（11）是短通道器件时，通过端子偏置来调节寄生电容器（24,26）的电容，可以实现非对称条件 。 通过偏置FET（11）的源极（14），漏极（16）和衬底（18）来控制浮置栅极（12）的电位。 电池（10）通过经由热载流子注入将电荷移动到浮动栅极（12）上被编程，通过经由隧道从浮动栅极（12）移动电荷并通过感测FET（11）的导通状态来读取。

公开(公告)号：US5892709A

公开(公告)日：1999-04-06

申请号：US853601

申请日：1997-05-09

申请人： Patrice M. Parris ,  Yee-Chaung See

发明人： Patrice M. Parris ,  Yee-Chaung See

IPC分类号： H01L21/8247 ,  G11C16/04 ,  G11C17/18 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/045 ,  G11C16/0441 ,  H01L27/115 ,  G11C2216/10

摘要： A single level gate NVM device (10) includes p-channel and n-channel floating gate FETs (12, 14), an erasing capacitor (26), and a programming capacitor (28). The NVM device (10) is programmed by applying a programming voltage to the programming capacitor (28) and applying a ground voltage to the sources of the FETs (12, 14). The NVM device (10) is erased by applying an erasing voltage to the erasing capacitor (26) and applying ground voltage to the sources of the FETs (12, 14) and to the programming capacitor (28). Data is read from the NVM device (10) by sensing a voltage level at the drains of the FETs (12, 14) while applying a logic high voltage to the source of the p-channel FET (12), a logic low voltage to the source of the n-channel FET (14), and a reading voltage to the programming capacitor (28).

摘要翻译： 单级门NVM器件（10）包括p沟道和n沟道浮置栅极FET（12,14），擦除电容器（26）和编程电容器（28）。 通过向编程电容器（28）施加编程电压并将接地电压施加到FET（12,14）的源极来对NVM器件（10）进行编程。 通过向擦除电容器（26）施加擦除电压并向FET（12,14）的源极和编程电容器（28）施加接地电压，擦除NVM器件（10）。 通过在FET（12,14）的漏极处感测电压电平同时向p沟道FET（12）的源施加逻辑高电压，从NVM器件（10）读取数据，逻辑低电压 n沟道FET（14）的源极和编程电容器（28）的读取电压。

公开(公告)号：US08963256B2

公开(公告)日：2015-02-24

申请号：US13004396

申请日：2011-01-11

申请人： Moaniss Zitouni ,  Patrice M. Parris

发明人： Moaniss Zitouni ,  Patrice M. Parris

IPC分类号： H01L21/00 ,  H01L27/092 ,  H01L21/8238

CPC分类号： H01L27/0921 ,  H01L21/823878

摘要： Latch-up of CMOS devices is improved by using a structure having electrically coupled but floating doped regions between the N-channel and P-channel devices. The doped regions desirably lie substantially parallel to the source-drain regions of the devices between the Pwell and Nwell regions in which the source-drain regions are located. A first (“N BAR”) doped region forms a PN junction with the Pwell, spaced apart from a source/drain region in the Pwell, and a second (“P BAR”) doped region forms a PN junction with the Nwell, spaced apart from a source/drain region in the Nwell. A further NP junction lies between the N BAR and P BAR regions. The N BAR and P BAR regions are ohmically coupled, preferably by a low resistance metal conductor, and otherwise floating with respect to the device or circuit reference potentials (e.g., Vss, Vdd).

摘要翻译： 通过使用在N沟道和P沟道器件之间具有电耦合但浮置的掺杂区域的结构来提高CMOS器件的锁存。 掺杂区域理想地基本上平行于源极 - 漏极区域所在的P阱和Nwell区域之间的器件的源极 - 漏极区域。 第一（“N BAR”）掺杂区域与P阱形成PN结，与P阱中的源/漏区间隔开，并且第二（“P BAR”）掺杂区域与Nwell形成PN结，间隔开 除了Nwell中的源/漏区外。 另外的NP连接点位于N BAR和P BAR区域之间。 N BAR和P BAR区域优选地通过低电阻金属导体欧姆耦合，否则相对于器件或电路参考电位（例如Vss，Vdd）浮置。

公开(公告)号：US07301187B2

公开(公告)日：2007-11-27

申请号：US11689313

申请日：2007-03-21

申请人： Edouard D. Defresart ,  Richard J. Desouza ,  Xin Lin ,  Jennifer H. Morrison ,  Patrice M. Parris ,  Moaniss Zitouni

发明人： Edouard D. Defresart ,  Richard J. Desouza ,  Xin Lin ,  Jennifer H. Morrison ,  Patrice M. Parris ,  Moaniss Zitouni

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/0847 ,  H01L29/7833 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92′) serially located between the channel (90) and the source (70, 70′) or drain (76, 76′). A buried region (96, 96′) of the same conductivity type as the drift space (92, 92′) and the source (70, 70′) or drain (76, 76′) is provided below the drift space (92, 92′), separated therefrom in depth by a narrow gap (94, 94′) and ohmically coupled to the source (70, 70′) or drain (76, 76′). Current flow (110) through the drift space produces a potential difference (Vt) across this gap (94, 94′). As the S-D voltage (Vo) and current (109, Io) increase, this difference (Vt) induces high field conduction between the drift space (92, 92′) and the buried region (96, 96′) and diverts part (112, It) of the S-D current (109, Io) through the buried region (96, 96′) and away from the near surface portions of the drift space (92, 92′) where breakdown generally occurs. Thus, BVdss is increased.

摘要翻译： 为具有增加的源 - 漏击穿电压（BVdss）的MOSFET（50,99,199）提供了方法和装置。 源极（S）（70）和漏极（D）（76）通过栅极（84）下面的沟道（90）和串联地位于沟道（90）之间的一个或多个载流子漂移空间（92,92'）间隔开 ）和源极（70,70'）或漏极（76,76'）。 与漂移空间（92,92'）和源极（70,70'）或漏极（76,76'）相同的导电类型的掩埋区域（96,96'）设置在漂移空间（92,92'）的下方， 92'），通过狭窄的间隙（94,94'）深度地分离，并且与欧姆耦合到源极（70,70'）或漏极（76,76'）。 穿过漂移空间的电流（110）在该间隙（94,94'）上产生电位差（Vt）。 随着SD电压（Vo）和电流（109，Io）的增加，该差值（Vt）引起漂移空间（92,92'）和掩埋区域（96,96'）之间的高场导通，并且转移部分 ，It）通过掩埋区域（96,96'）并远离漂移空间（92,92'）的通常发生击穿的漂移空间（92,92'）的近表面部分的SD电流（109，Io）。 因此，BVdss增加。