公开(公告)号：US09741793B2

公开(公告)日：2017-08-22

申请号：US13448062

申请日：2012-04-16

申请人： Patrice M. Parris ,  Weize Chen

发明人： Patrice M. Parris ,  Weize Chen

IPC分类号： H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/40

CPC分类号： H01L29/0847 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/7835

摘要： An electronic apparatus includes a semiconductor substrate and first and second transistors disposed in the semiconductor substrate. The first transistor includes a channel region and a drain region adjacent the channel region. The second transistor includes a channel region, a false drain region adjacent the channel region, and a drain region electrically coupled to the channel region by a drift region such that the second transistor is configured for operation at a higher voltage level than the first transistor. The respective channel regions of the first and second transistors have a common configuration characteristic.

公开(公告)号：US09537000B2

公开(公告)日：2017-01-03

申请号：US13792876

申请日：2013-03-11

申请人： Weize Chen ,  Patrice M. Parris

发明人： Weize Chen ,  Patrice M. Parris

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08

CPC分类号： H01L29/7816 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

摘要： A semiconductor device includes a substrate having a surface, a composite body region disposed in the substrate, having a first conductivity type, and comprising a body contact region at the surface of the substrate and a well in which a channel is formed during operation, a source region disposed in the semiconductor substrate adjacent the composite body region and having a second conductivity type, and an isolation region disposed between the body contact region and the source region. The composite body region further includes a body conduction path region contiguous with and under the source region, and the body conduction path region has a higher dopant concentration level than the well.

摘要翻译： 半导体器件包括具有表面的衬底，设置在衬底中的复合体区域，具有第一导电类型，并且包括在衬底的表面处的体接触区域和在操作期间形成沟道的阱， 源极区域，设置在与所述复合体区域相邻并具有第二导电类型的所述半导体衬底中;以及隔离区域，设置在所述本体接触区域和所述源极区域之间。 复合体区域还包括与源极区域相邻并且在源极区域附近的体导电路径区域，并且身体传导路径区域具有比阱更高的掺杂剂浓度水平。

公开(公告)号：US09231120B2

公开(公告)日：2016-01-05

申请号：US13537299

申请日：2012-06-29

申请人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

发明人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

IPC分类号： H01L29/872 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06

CPC分类号： H01L29/872 ,  H01L29/0692 ,  H01L29/417 ,  H01L29/66143

摘要： A Schottky diode includes a device structure having a central portion and a plurality of fingers. Distal portions of the fingers overlie leakage current control (LCC) regions. An LCC region is relatively narrow and deep, terminating in proximity to a buried layer of like polarity. Under reverse bias, depletion regions forming in an active region lying between the buried layer and the LCC regions occupy the entire extent of the active region and thereby provide a carrier depleted wall. An analogous depletion region occurs in the active region residing between any pair of adjacent fingers. If the fingers include latitudinal oriented fingers and longitudinal oriented fingers, depletion region blockades in three different orthogonal orientations may occur. The formation of the LCC regions may include the use of a high dose, low energy phosphorous implant using an LCC implant mask and the isolation structures as an additional hard mask.

摘要翻译： 肖特基二极管包括具有中心部分和多个指状物的器件结构。 手指的远端覆盖泄漏电流控制（LCC）区域。 LCC区域相对较窄和深，终止于类似极性的掩埋层附近。 在反向偏压下，在位于掩埋层和LCC区域之间的有源区域中形成的耗尽区域占据有源区域的整个范围，从而提供载流子耗尽的壁。 类似的耗尽区发生在驻留在任何一对相邻手指之间的有源区域中。 如果手指包括纬向取向的指状物和纵向取向的指状物，则可能发生三个不同正交取向的耗尽区域封锁。 LCC区域的形成可以包括使用使用LCC植入物掩模的高剂量，低能量磷植入物以及作为附加硬掩模的隔离结构。

公开(公告)号：US20150316503A1

公开(公告)日：2015-11-05

申请号：US14265622

申请日：2014-04-30

申请人： Md M. Hoque ,  Patrice M. Parris ,  Weize Chen ,  Richard J. De Souza

发明人： Md M. Hoque ,  Patrice M. Parris ,  Weize Chen ,  Richard J. De Souza

IPC分类号： G01N27/414 ,  H01L29/78 ,  H01L29/66

CPC分类号： G01N27/4148 ,  H01L21/28282 ,  H01L27/11531 ,  H01L29/66 ,  H01L29/66409 ,  H01L29/78 ,  H01L29/788

摘要： A differential pair sensing circuit (300) includes control gates (306, 316) for separately programming a reference transistor (350) and a chemically-sensitive transistor (351) to a desired threshold voltage Vt to eliminate the mismatch between the transistors in order to increase the sensitivity and/or accuracy of the sensing circuit without increasing the circuit size.

摘要翻译： 差分对检测电路（300）包括用于将参考晶体管（350）和化学敏感晶体管（351）单独编程为期望阈值电压Vt的控制栅极（306,316），以消除晶体管之间的失配，以便 提高感测电路的灵敏度和/或精度，而不增加电路尺寸。

公开(公告)号：US08735950B2

公开(公告)日：2014-05-27

申请号：US13605357

申请日：2012-09-06

申请人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

发明人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

IPC分类号： H01L29/66

CPC分类号： H01L29/66893 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/08 ,  H01L29/1066 ,  H01L29/107 ,  H01L29/66143 ,  H01L29/872

摘要： A device includes a semiconductor substrate, first and second electrodes supported by the semiconductor substrate, laterally spaced from one another, and disposed at a surface of the semiconductor substrate to form an Ohmic contact and a Schottky junction, respectively. The device further includes a conduction path region in the semiconductor substrate, having a first conductivity type, and disposed along a conduction path between the first and second electrodes, a buried region in the semiconductor substrate having a second conductivity type and disposed below the conduction path region, and a device isolating region electrically coupled to the buried region, having the second conductivity type, and defining a lateral boundary of the device. The device isolating region is electrically coupled to the second electrode such that a voltage at the second electrode during operation is applied to the buried region to deplete the conduction path region.

摘要翻译： 一种器件包括半导体衬底，由半导体衬底支撑的第一和第二电极，彼此横向间隔开，并分别设置在半导体衬底的表面以形成欧姆接触和肖特基结。 该器件还包括半导体衬底中的导电通路区域，具有第一导电类型，并且沿第一和第二电极之间的导电路径设置，半导体衬底中的具有第二导电类型并设置在导电路径下方的掩埋区域 以及电耦合到所述掩埋区域的器件隔离区域，具有所述第二导电类型，并且限定所述器件的横向边界。 器件隔离区域电耦合到第二电极，使得在操作期间第二电极处的电压被施加到掩埋区域以耗尽导电路径区域。

公开(公告)号：US20140001473A1

公开(公告)日：2014-01-02

申请号：US13538565

申请日：2012-06-29

申请人： WEIZE CHEN ,  HUBERT M. BODE ,  RICHARD J. DE SOUZA ,  PATRICE M. PARRIS

发明人： WEIZE CHEN ,  HUBERT M. BODE ,  RICHARD J. DE SOUZA ,  PATRICE M. PARRIS

IPC分类号： H01L27/088 ,  H01L21/02

CPC分类号： H01L27/0629 ,  H01L27/0288 ,  H01L29/04 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66681 ,  H01L29/7818 ,  H01L29/782 ,  H01L29/861 ,  H01L29/872

摘要： Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a source region of the first conductivity type, and the diode circuit is connected between the isolation structure and the source region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s).

摘要翻译： 半导体器件和驱动电路的实施例包括具有第一导电类型的半导体衬底，隔离结构（包括沉陷区和掩埋层），由隔离结构包含的衬底区域内的有源器件和二极管电路。 掩埋层位于顶部衬底表面下方，并且具有第二导电类型。 沉降片区域在顶部衬底表面和掩埋层之间延伸，并且具有第二导电类型。 有源器件包括第一导电类型的源极区域，二极管电路连接在隔离结构和源极区域之间。 二极管电路可以包括一个或多个肖特基二极管和/或PN结二极管。 在另外的实施例中，二极管电路可以包括与肖特基和/或PN二极管串联和/或并联的一个或多个电阻网络。

公开(公告)号：US20130270606A1

公开(公告)日：2013-10-17

申请号：US13448994

申请日：2012-04-17

申请人： Weize Chen ,  Hubert M. Bode ,  Richard J. De Souza ,  Patrice M. Parris

发明人： Weize Chen ,  Hubert M. Bode ,  Richard J. De Souza ,  Patrice M. Parris

IPC分类号： H01L29/06 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7823 ,  H01L21/2253 ,  H01L29/0626 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7824 ,  H01L29/7835

摘要： A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. The device isolating region and the body region are spaced from one another to establish a first breakdown voltage lower than a second breakdown voltage in the conduction path.

摘要翻译： 一种器件包括具有第一导电类型的半导体衬底，半导体衬底中的器件隔离区，限定有源区，并具有第二导电类型，有源区中的体区，并具有第一导电类型，漏极 区域，并且与身体区域间隔开以限定器件的导电路径，漏极区域具有第二导电类型。 器件隔离区域和体区域彼此间隔开以建立低于导通路径中的第二击穿电压的第一击穿电压。

公开(公告)号：US08344443B2

公开(公告)日：2013-01-01

申请号：US12109736

申请日：2008-04-25

申请人： Weize Chen ,  Richard J. De Souza ,  Xin Lin ,  Patrice M. Parris

发明人： Weize Chen ,  Richard J. De Souza ,  Xin Lin ,  Patrice M. Parris

IPC分类号： H01L29/788 ,  H01L27/115 ,  H01L21/8247

CPC分类号： H01L29/7881 ,  G11C16/10 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42324

摘要： A single-poly non-volatile memory includes a PMOS select transistor (210) formed with a select gate (212), and P+ source and drain regions (211, 213) formed in a shared n-well region (240), a serially connected PMOS floating gate transistor (220) formed with part of a p-type floating gate layer (222) and P+ source and drain regions (221, 223) formed in the shared n-well region (240), and a coupling capacitor (230) formed over a p-well region (250) and connected to the PMOS floating gate transistor (220), where the coupling capacitor (230) includes a first capacitor plate formed with a second part of the p-type floating gate layer (222) and an underlying portion of the p-well region (250).

摘要翻译： 单多晶非易失性存储器包括形成有选择栅极（212）的PMOS选择晶体管（210），以及形成在共享的n阱区域（240）中的P +源区和漏区（211,213） 形成有形成在共用n阱区域（240）中的p型浮栅（222）和P +源区和漏区（221,223）的一部分的连接PMOS浮栅晶体管（220）和耦合电容器 230），其形成在p阱区（250）上并连接到PMOS浮栅晶体管（220），其中耦合电容器（230）包括形成有p型浮栅的第二部分的第一电容器板（ 222）和p阱区（250）的下层部分。

公开(公告)号：US07740805B2

公开(公告)日：2010-06-22

申请号：US11095338

申请日：2005-03-31

申请人： Patrice M. Parris

发明人： Patrice M. Parris

IPC分类号： B01L3/00

CPC分类号： B01L3/502715 ,  B01L3/502707 ,  B01L2200/10 ,  B01L2200/12 ,  B01L2300/023 ,  B01L2300/024 ,  B01L2300/0627 ,  B01L2300/0645 ,  B01L2400/0406 ,  B01L2400/0415 ,  G01N2035/00158

摘要： A device for analyzing a fluid sample is provided. The device includes a substrate, a trench formed in said substrate, and a processor. The trench includes a channel, a sample chamber, and a reagent chamber, each in fluid communication with each another. The sample chamber is configured to receive the fluid sample. The processor is integrally formed in the substrate and is in communication with the trench. The processor is configured to analyze the fluid sample. Methods for manufacturing the device are also provided.

摘要翻译： 提供了用于分析流体样品的装置。 该器件包括衬底，形成在所述衬底中的沟槽和处理器。 沟槽包括各自彼此流体连通的通道，样品室和试剂室。 样品室被配置为接收流体样品。 处理器一体地形成在基板中并且与沟槽连通。 处理器配置为分析流体样品。 还提供了用于制造该装置的方法。

公开(公告)号：US5892379A

公开(公告)日：1999-04-06

申请号：US867661

申请日：1997-06-02

申请人： Juan Buxo ,  Andreas A. Wild ,  Gary H. Loechelt ,  Thomas E. Zirkle ,  E. James Prendergast ,  Patrice M. Parris

发明人： Juan Buxo ,  Andreas A. Wild ,  Gary H. Loechelt ,  Thomas E. Zirkle ,  E. James Prendergast ,  Patrice M. Parris

IPC分类号： H03K17/0812 ,  H03K19/003 ,  H03B1/00 ,  H03K17/687

CPC分类号： H03K17/08122 ,  H03K19/00315

摘要： A circuit and method protect a transistor (68, 70) from damage when controlling an input signal (V.sub.PROG) that exceeds a gate to channel stress voltage of the transistor. A small, low current protection transistor (64, 66) is serially coupled to the gate electrode of the transistor being protected. The gate of the protection transistor is biased to a voltage (V.sub.P, V.sub.N) of lower magnitude than the input signal to limit the voltage applied to the gate of the protected transistor to a value within the stress voltage of the protected transistor.

摘要翻译： 当控制超过晶体管的栅极至沟道应力电压的输入信号（VPROG）时，电路和方法保护晶体管（68,70）免受损坏。 一个小的低电流保护晶体管（64,66）串联耦合到被保护的晶体管的栅电极。 保护晶体管的栅极被偏置为比输入信号更低的电压（VP，VN），以将施加到受保护晶体管的栅极的电压限制在受保护晶体管的应力电压内的值。