公开(公告)号：US20110101465A1

公开(公告)日：2011-05-05

申请号：US13004396

申请日：2011-01-11

申请人： Moaniss Zitouni ,  Patrice M. Parris

发明人： Moaniss Zitouni ,  Patrice M. Parris

IPC分类号： H01L27/092

CPC分类号： H01L27/0921 ,  H01L21/823878

摘要： Latch-up of CMOS devices is improved by using a structure having electrically coupled but floating doped regions between the N-channel and P-channel devices. The doped regions desirably lie substantially parallel to the source-drain regions of the devices between the Pwell and Nwell regions in which the source-drain regions are located. A first (“N BAR”) doped region forms a PN junction with the Pwell, spaced apart from a source/drain region in the Pwell, and a second (“P BAR”) doped region forms a PN junction with the Nwell, spaced apart from a source/drain region in the Nwell. A further NP junction lies between the N BAR and P BAR regions. The N BAR and P BAR regions are ohmically coupled, preferably by a low resistance metal conductor, and otherwise floating with respect to the device or circuit reference potentials (e.g., Vss, Vdd).

摘要翻译： 通过使用在N沟道和P沟道器件之间具有电耦合但浮置的掺杂区域的结构来提高CMOS器件的锁存。 掺杂区域理想地基本上平行于源极 - 漏极区域所在的P阱和Nwell区域之间的器件的源极 - 漏极区域。 第一（“N BAR”）掺杂区域与P阱形成PN结，与P阱中的源/漏区间隔开，并且第二（“P BAR”）掺杂区域与Nwell形成PN结，间隔开 除了Nwell中的源/漏区外。 另外的NP连接点位于N BAR和P BAR区域之间。 N BAR和P BAR区域优选地通过低电阻金属导体欧姆耦合，否则相对于器件或电路参考电位（例如Vss，Vdd）浮置。

公开(公告)号：US07892907B2

公开(公告)日：2011-02-22

申请号：US12262922

申请日：2008-10-31

申请人： Moaniss Zitouni ,  Patrice M. Parris

发明人： Moaniss Zitouni ,  Patrice M. Parris

IPC分类号： H01L21/00

CPC分类号： H01L27/0921 ,  H01L21/823878

摘要： Latch-up of CMOS devices (20, 20′) is improved by using a structure (40, 40′, 80) having electrically coupled but floating doped regions (64, 64′; 65, 65′) between the N-channel (44) and P-channel (45) devices. The doped regions (64, 64′; 65, 65′) desirably lie substantially parallel to the source-drain regions (422, 423; 432, 433) of the devices (44, 45) between the Pwell (42) and Nwell (43) regions in which the source-drain regions (422, 423; 432, 433) are located. A first (“N BAR”) doped region (64, 64′) forms a PN junction (512) with the Pwell (42), spaced apart from a source/drain region (423) in the Pwell (42), and a second (“P BAR”) doped region (55, 55′) forms a PN junction (513) with the Nwell (43), spaced apart from a source/drain region (433) in the Nwell (43). A further NP junction (511) lies between the N BAR (64) and P BAR (65) regions. The N BAR (64) and P BAR (65) regions are ohmically coupled, preferably by a low resistance metal conductor (62), and otherwise floating with respect to the device or circuit reference potentials (e.g., Vss, Vdd).

摘要翻译： 通过使用具有电耦合但浮置的掺杂区域（64,64'; 65,65'）的结构（40,40'，80）来改善CMOS器件（20,20'）的锁存，N结构 44）和P沟道（45）器件。 掺杂区域（64,64'; 65,65'）理想地位于Pwell（42）和Nwell（...）之间的器件（44,45）的源极 - 漏极区域（422,423; 432,433） 43）源极 - 漏极区域（422,423,432,433）所在的区域。 第一（“N BAR”）掺杂区域（64,64'）与Pwell（42）中的P阱（42）形成PN结（512），与Pwell（42）中的源极/漏极区域（423）间隔开，并且 第二（“P BAR”）掺杂区域（55,55'）与N阱（43）中的源极/漏极区域（433）间隔开，形成具有N阱（43）的PN结（513）。 另外的NP结（511）位于N BAR（64）和P BAR（65）区之间。 N BAR（64）和P BAR（65）区域优选地通过低电阻金属导体（62）欧姆耦合，并且否则相对于器件或电路参考电位（例如，Vss，Vdd）浮置。

公开(公告)号：US08963256B2

公开(公告)日：2015-02-24

申请号：US13004396

申请日：2011-01-11

申请人： Moaniss Zitouni ,  Patrice M. Parris

发明人： Moaniss Zitouni ,  Patrice M. Parris

IPC分类号： H01L21/00 ,  H01L27/092 ,  H01L21/8238

CPC分类号： H01L27/0921 ,  H01L21/823878

摘要： Latch-up of CMOS devices is improved by using a structure having electrically coupled but floating doped regions between the N-channel and P-channel devices. The doped regions desirably lie substantially parallel to the source-drain regions of the devices between the Pwell and Nwell regions in which the source-drain regions are located. A first (“N BAR”) doped region forms a PN junction with the Pwell, spaced apart from a source/drain region in the Pwell, and a second (“P BAR”) doped region forms a PN junction with the Nwell, spaced apart from a source/drain region in the Nwell. A further NP junction lies between the N BAR and P BAR regions. The N BAR and P BAR regions are ohmically coupled, preferably by a low resistance metal conductor, and otherwise floating with respect to the device or circuit reference potentials (e.g., Vss, Vdd).

摘要翻译： 通过使用在N沟道和P沟道器件之间具有电耦合但浮置的掺杂区域的结构来提高CMOS器件的锁存。 掺杂区域理想地基本上平行于源极 - 漏极区域所在的P阱和Nwell区域之间的器件的源极 - 漏极区域。 第一（“N BAR”）掺杂区域与P阱形成PN结，与P阱中的源/漏区间隔开，并且第二（“P BAR”）掺杂区域与Nwell形成PN结，间隔开 除了Nwell中的源/漏区外。 另外的NP连接点位于N BAR和P BAR区域之间。 N BAR和P BAR区域优选地通过低电阻金属导体欧姆耦合，否则相对于器件或电路参考电位（例如Vss，Vdd）浮置。

公开(公告)号：US20110261500A1

公开(公告)日：2011-10-27

申请号：US12765575

申请日：2010-04-22

申请人： Patrice M. Parris ,  Richard J. De Souza ,  Weize Chen ,  Moaniss Zitouni

发明人： Patrice M. Parris ,  Richard J. De Souza ,  Weize Chen ,  Moaniss Zitouni

IPC分类号： H01G4/00 ,  B05D5/12

CPC分类号： H01G4/33 ,  H01G4/232 ,  H01L23/5223 ,  H01L28/86 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： Apparatus and related fabrication methods are provided for capacitor structures. One embodiment of a capacitor structure comprises a plurality of consecutive metal layers and another metal layer. Each via layer of a plurality of via layers is interposed between metal layers of the plurality of metal layers. The plurality of metal layers and the plurality of via layers are cooperatively configured to provide a first plurality of vertical conductive structures corresponding to a first electrode and a second plurality of vertical conductive structures corresponding to a second electrode. The plurality of consecutive metal layers form a plurality of vertically-aligned regions and provide intralayer electrical interconnections among the first plurality of vertical conductive structures. The first metal layer provides an intralayer electrical interconnection among the second plurality of vertical conductive structures, wherein each vertically-aligned region has a vertical conductive structure of the second plurality of vertical conductive structures disposed therein.

摘要翻译： 为电容器结构提供了装置和相关的制造方法。 电容器结构的一个实施例包括多个连续的金属层和另一个金属层。 多个通孔层的每个通孔层插入在多个金属层的金属层之间。 多个金属层和多个通孔层协作地构造成提供对应于对应于第二电极的第一电极和第二多个垂直导电结构的第一多个垂直导电结构。 多个连续的金属层形成多个垂直排列的区域，并且在第一多个垂直导电结构之间提供层间电互连。 第一金属层在第二多个垂直导电结构之间提供内层电互连，其中每个垂直对齐区域具有设置在其中的第二多个垂直导电结构的垂直导电结构。

公开(公告)号：US07301187B2

公开(公告)日：2007-11-27

申请号：US11689313

申请日：2007-03-21

申请人： Edouard D. Defresart ,  Richard J. Desouza ,  Xin Lin ,  Jennifer H. Morrison ,  Patrice M. Parris ,  Moaniss Zitouni

发明人： Edouard D. Defresart ,  Richard J. Desouza ,  Xin Lin ,  Jennifer H. Morrison ,  Patrice M. Parris ,  Moaniss Zitouni

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/0847 ,  H01L29/7833 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92′) serially located between the channel (90) and the source (70, 70′) or drain (76, 76′). A buried region (96, 96′) of the same conductivity type as the drift space (92, 92′) and the source (70, 70′) or drain (76, 76′) is provided below the drift space (92, 92′), separated therefrom in depth by a narrow gap (94, 94′) and ohmically coupled to the source (70, 70′) or drain (76, 76′). Current flow (110) through the drift space produces a potential difference (Vt) across this gap (94, 94′). As the S-D voltage (Vo) and current (109, Io) increase, this difference (Vt) induces high field conduction between the drift space (92, 92′) and the buried region (96, 96′) and diverts part (112, It) of the S-D current (109, Io) through the buried region (96, 96′) and away from the near surface portions of the drift space (92, 92′) where breakdown generally occurs. Thus, BVdss is increased.

摘要翻译： 为具有增加的源 - 漏击穿电压（BVdss）的MOSFET（50,99,199）提供了方法和装置。 源极（S）（70）和漏极（D）（76）通过栅极（84）下面的沟道（90）和串联地位于沟道（90）之间的一个或多个载流子漂移空间（92,92'）间隔开 ）和源极（70,70'）或漏极（76,76'）。 与漂移空间（92,92'）和源极（70,70'）或漏极（76,76'）相同的导电类型的掩埋区域（96,96'）设置在漂移空间（92,92'）的下方， 92'），通过狭窄的间隙（94,94'）深度地分离，并且与欧姆耦合到源极（70,70'）或漏极（76,76'）。 穿过漂移空间的电流（110）在该间隙（94,94'）上产生电位差（Vt）。 随着SD电压（Vo）和电流（109，Io）的增加，该差值（Vt）引起漂移空间（92,92'）和掩埋区域（96,96'）之间的高场导通，并且转移部分 ，It）通过掩埋区域（96,96'）并远离漂移空间（92,92'）的通常发生击穿的漂移空间（92,92'）的近表面部分的SD电流（109，Io）。 因此，BVdss增加。

公开(公告)号：US20090127587A1

公开(公告)日：2009-05-21

申请号：US12361944

申请日：2009-01-29

申请人： Patrice M. Parris ,  Weize Chen ,  John M. McKenna ,  Jennifer H. Morrison ,  Moaniss Zitouni ,  Richard J. De Souza

发明人： Patrice M. Parris ,  Weize Chen ,  John M. McKenna ,  Jennifer H. Morrison ,  Moaniss Zitouni ,  Richard J. De Souza

IPC分类号： H01L29/78 ,  H01L29/86 ,  H01L25/07

CPC分类号： H01L27/112 ,  H01L23/5252 ,  H01L27/11206 ,  H01L2924/0002 ,  Y10S438/981 ,  H01L2924/00

摘要： A tunable antifuse element (102, 202, 204, 504, 952) includes a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer (110) disposed between the gate electrode (104) and the active area (106). The dielectric layer (110) includes a tunable stepped structure (127). During operation, a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the dielectric layer (110) and a rupture of the dielectric layer (110) in a rupture region (130). The dielectric layer (110) is tunable by varying the stepped layer thicknesses and the geometry of the layer.

摘要翻译： 可调谐反熔断元件（102,202,204,504,952）包括具有形成在表面中的有源区域（106）的基板材料（101），栅电极（104），其至少部分位于有源区域 （106）和设置在栅电极（104）和有源区（106）之间的电介质层（110）。 电介质层（110）包括可调阶梯结构（127）。 在操作期间，施加在栅极电极（104）和有源区域（106）之间的电压产生穿过电介质层（110）的电流路径以及在破裂区域（130）中电介质层（110）的破裂。 电介质层（110）可以通过改变阶梯层厚度和层的几何形状来调节。

公开(公告)号：US07528015B2

公开(公告)日：2009-05-05

申请号：US11169962

申请日：2005-06-28

申请人： Patrice M. Parris ,  Weize Chen ,  John M. McKenna ,  Jennifer H. Morrison ,  Moaniss Zitouni ,  Richard J. De Souza

发明人： Patrice M. Parris ,  Weize Chen ,  John M. McKenna ,  Jennifer H. Morrison ,  Moaniss Zitouni ,  Richard J. De Souza

IPC分类号： H01L21/82 ,  H01L21/44 ,  H01L21/31

CPC分类号： H01L27/112 ,  H01L23/5252 ,  H01L27/11206 ,  H01L2924/0002 ,  Y10S438/981 ,  H01L2924/00

摘要： A tunable antifuse element (102, 202, 204, 504, 952) and method of fabricating the tunable antifuse element, including a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer (110) disposed between the gate electrode (104) and the active area (106). The dielectric layer (110) including the fabrication of one of a tunable stepped structure (127). During operation, a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the dielectric layer (110) and a rupture of the dielectric layer (110) in a plurality of rupture regions (130). The dielectric layer (110) is tunable by varying the stepped layer thicknesses and the geometry of the layer.

摘要翻译： 一种可调谐反熔断元件（102,202,204,504,952）和制造可调谐反熔丝元件的方法，包括在表面上形成有源区（106）的基片材料（101），具有 位于有源区域（106）上方的至少一部分，和设置在栅电极（104）和有源区域（106）之间的电介质层（110）。 介电层（110）包括制造可调阶梯结构（127）之一。 在操作期间，施加在栅极电极（104）和有源区域（106）之间的电压产生穿过介电层（110）的电流路径，并且多个断裂区域（130）中的电介质层（110）的破裂， 。 电介质层（110）可以通过改变阶梯层厚度和层的几何形状来调节。

公开(公告)号：US20100109090A1

公开(公告)日：2010-05-06

申请号：US12262922

申请日：2008-10-31

申请人： Moaniss Zitouni ,  Patrice M. Parris

发明人： Moaniss Zitouni ,  Patrice M. Parris

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L27/0921 ,  H01L21/823878

摘要： Latch-up of CMOS devices (20, 20′) is improved by using a structure (40, 40′, 80) having electrically coupled but floating doped regions (64, 64′; 65, 65′) between the N-channel (44) and P-channel (45) devices. The doped regions (64, 64′; 65, 65′) desirably lie substantially parallel to the source-drain regions (422, 423; 432, 433) of the devices (44, 45) between the Pwell (42) and Nwell (43) regions in which the source-drain regions (422, 423; 432, 433) are located. A first (“N BAR”) doped region (64, 64′) forms a PN junction (512) with the Pwell (42), spaced apart from a source/drain region (423) in the Pwell (42), and a second (“P BAR”) doped region (55, 55′) forms a PN junction (513) with the Nwell (43), spaced apart from a source/drain region (433) in the Nwell (43). A further NP junction (511) lies between the N BAR (64) and P BAR (65) regions. The N BAR (64) and P BAR (65) regions are ohmically coupled, preferably by a low resistance metal conductor (62), and otherwise floating with respect to the device or circuit reference potentials (e.g., Vss, Vdd).

摘要翻译： 通过使用具有电耦合但浮置的掺杂区域（64,64'; 65,65'）的结构（40,40'，80）来改善CMOS器件（20,20'）的锁存，N结构 44）和P沟道（45）器件。 掺杂区域（64,64'; 65,65'）理想地位于Pwell（42）和Nwell（...）之间的器件（44,45）的源极 - 漏极区域（422,423; 432,433） 43）源极 - 漏极区域（422,423,432,433）所在的区域。 第一（“N BAR”）掺杂区域（64,64'）与Pwell（42）中的P阱（42）形成PN结（512），与Pwell（42）中的源极/漏极区域（423）间隔开，并且 第二（“P BAR”）掺杂区域（55,55'）与N阱（43）中的源极/漏极区域（433）间隔开，形成具有N阱（43）的PN结（513）。 另外的NP结（511）位于N BAR（64）和P BAR（65）区之间。 N BAR（64）和P BAR（65）区域优选地通过低电阻金属导体（62）欧姆耦合，并且否则相对于器件或电路参考电位（例如，Vss，Vdd）浮置。

公开(公告)号：US07700996B2

公开(公告)日：2010-04-20

申请号：US12361944

申请日：2009-01-29

申请人： Patrice M. Parris ,  Weize Chen ,  John M. McKenna ,  Jennifer H. Morrison ,  Moaniss Zitouni ,  Richard J. De Souza

发明人： Patrice M. Parris ,  Weize Chen ,  John M. McKenna ,  Jennifer H. Morrison ,  Moaniss Zitouni ,  Richard J. De Souza

IPC分类号： H01L29/94

CPC分类号： H01L27/112 ,  H01L23/5252 ,  H01L27/11206 ,  H01L2924/0002 ,  Y10S438/981 ,  H01L2924/00

摘要： A tunable antifuse element (102, 202, 204, 504, 952) includes a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer (110) disposed between the gate electrode (104) and the active area (106). The dielectric layer (110) includes a tunable stepped structure (127). During operation, a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the dielectric layer (110) and a rupture of the dielectric layer (110) in a rupture region (130). The dielectric layer (110) is tunable by varying the stepped layer thicknesses and the geometry of the layer.

摘要翻译： 可调谐反熔断元件（102,202,204,504,952）包括具有形成在表面中的有源区域（106）的基板材料（101），栅电极（104），其至少部分位于有源区域 （106）和设置在栅电极（104）和有源区（106）之间的电介质层（110）。 电介质层（110）包括可调阶梯结构（127）。 在操作期间，施加在栅极电极（104）和有源区域（106）之间的电压产生穿过电介质层（110）的电流路径以及在破裂区域（130）中电介质层（110）的破裂。 电介质层（110）可以通过改变阶梯层厚度和层的几何形状来调节。

公开(公告)号：US07211477B2

公开(公告)日：2007-05-01

申请号：US11124469

申请日：2005-05-06

申请人： Edouard D. de Frésart ,  Richard J. De Souza ,  Xin Lin ,  Jennifer H. Morrison ,  Patrice M. Parris ,  Moaniss Zitouni

发明人： Edouard D. de Frésart ,  Richard J. De Souza ,  Xin Lin ,  Jennifer H. Morrison ,  Patrice M. Parris ,  Moaniss Zitouni

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/0847 ,  H01L29/7833 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92′) serially located between the channel (90) and the source (70, 70′) or drain (76, 76′). A buried region (96, 96′) of the same conductivity type as the drift space (92, 92′) and the source (70, 70′) or drain (76, 76′) is provided below the drift space (92, 92′), separated therefrom in depth by a narrow gap (94, 94′) and ohmically coupled to the source (70, 70′) or drain (76, 76′). Current flow (110) through the drift space produces a potential difference (Vt) across this gap (94, 94′). As the S-D voltage (Vo) and current (109, Io) increase, this difference (Vt) induces high field conduction between the drift space (92, 92′) and the buried region (96, 96′) and diverts part (112, It) of the S-D current (109, Io) through the buried region (96, 96′) and away from the near surface portions of the drift space (92, 92′) where breakdown generally occurs. Thus, BVdss is increased.