公开(公告)号：US20120063284A1

公开(公告)日：2012-03-15

申请号：US13186146

申请日：2011-07-19

申请人： George Mathew ,  Ming Jin ,  Shaohua Yang ,  Erich F. Haratsch

发明人： George Mathew ,  Ming Jin ,  Shaohua Yang ,  Erich F. Haratsch

IPC分类号： G11B27/36

CPC分类号： G11B20/10046 ,  G11B5/012 ,  G11B5/09 ,  G11B19/045 ,  G11B20/10398 ,  G11B20/1217 ,  G11B2020/10759 ,  G11B2020/1232 ,  G11B2020/1298 ,  G11B2220/2516

摘要： Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is discussed that includes: a data buffer, an inter-track interference response circuit, an inter-track interference signal estimator circuit, and a sync mark detector circuit. The data buffer is operable to store a previous track data set that includes a first sync pattern. The inter-track interference response circuit is operable to estimate an inter-track interference response from the previous track data set based at least in part on the previous track data set and a current track data set. The current track data set includes a second sync pattern. The inter-track interference signal estimator circuit is operable to calculate an inter-track interference from the previous track data set based at least in part on the previous track data set and the inter-track interference response from the previous track data set. The sync mark detector circuit operable to identify the first sync pattern in the inter-track interference from the previous track data set in the current track data set.

摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 作为示例，讨论了包括数据缓冲器，轨道间干扰响应电路，轨道间干扰信号估计器电路和同步标记检测器电路的数据处理电路。 数据缓冲器可操作以存储包括第一同步模式的先前轨迹数据集。 轨道间干扰响应电路可用于至少部分地基于先前的轨道数据集和当前轨道数据集来估计来自先前轨道数据集的轨道间干扰响应。 当前轨道数据集包括第二同步模式。 轨道间干扰信号估计器电路可用于至少部分地基于先前的轨道数据集和来自前一轨道数据集的轨道间干扰响应来计算来自前一轨迹数据集的轨道间干扰。 同步标记检测器电路可用于识别来自当前轨道数据集中的先前轨道数据集的轨道间干扰中的第一同步模式。

公开(公告)号：US20120063024A1

公开(公告)日：2012-03-15

申请号：US13186197

申请日：2011-07-19

申请人： George Mathew ,  Jongseung Park ,  Shaohua Yang ,  Erich F. Haratsch ,  Ming Jin

发明人： George Mathew ,  Jongseung Park ,  Shaohua Yang ,  Erich F. Haratsch ,  Ming Jin

IPC分类号： G11B5/02

CPC分类号： G11B20/10046 ,  G11B5/012 ,  G11B5/09 ,  G11B19/045 ,  G11B20/10398 ,  G11B20/1217 ,  G11B2020/10759 ,  G11B2020/1232 ,  G11B2020/1298 ,  G11B2220/2516

摘要： Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is discussed that includes an inter-track interference determination circuit operable to calculate an inter-track interference from a previous track data set based at least in part on the previous track data set and a current track data set. The previous track data set includes a gap. A portion of the data in the previous track data set corresponds to a previous track on a storage medium, and the data in the previous track data set corresponding to the gap corresponds to a track preceding a previous track.

摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 作为示例，讨论了包括轨道间干扰确定电路的数据处理电路，其可操作以至少部分地基于先前的轨道数据集和当前轨道数据集来计算来自先前轨道数据集的轨道间干扰 。 先前的轨道数据集包括间隙。 前一轨道数据集中的一部分数据对应于存储介质上的先前磁道，并且与该间隙相对应的先前磁道数据集中的数据对应于先前磁道之前的磁迹。

公开(公告)号：US20120063023A1

公开(公告)日：2012-03-15

申请号：US13186213

申请日：2011-07-19

申请人： George Mathew ,  Jongseung Park ,  Shaohua Yang ,  Erich F. Haratsch

发明人： George Mathew ,  Jongseung Park ,  Shaohua Yang ,  Erich F. Haratsch

IPC分类号： G11B5/09

CPC分类号： G11B20/10046 ,  G11B5/012 ,  G11B5/09 ,  G11B19/045 ,  G11B20/10398 ,  G11B20/1217 ,  G11B2020/10759 ,  G11B2020/1232 ,  G11B2020/1298 ,  G11B2220/2516

摘要： Various embodiments of the present invention provide systems and methods for data processing. As an example, a block-wise data processing circuit is discussed that includes: a data buffer, an inter-track interference response circuit, and an inter-track interference signal estimator circuit. The data buffer is operable to store a previous track data set corresponding to a block. The inter-track interference response circuit is operable to estimate an inter-track interference response from the previous track data set across the block based at least in part on the previous track data set and a current track data set. The inter-track interference signal estimator circuit is operable to calculate an inter-track interference from the previous track data set across the block based at least in part on the previous track data set and the inter-track interference response from the previous track data set.

摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 作为示例，讨论了包括数据缓冲器，轨道间干扰响应电路和轨道间干扰信号估计器电路的块状数据处理电路。 数据缓冲器可操作以存储对应于块的先前轨道数据集。 轨道间干扰响应电路可操作以至少部分地基于先前的轨道数据集和当前轨道数据集来估计来自块的前一轨道数据集的轨道间干扰响应。 轨道间干扰信号估计器电路可操作以至少部分地基于先前的轨道数据集和来自前一轨道数据集的轨道间干扰响应来计算跨越块的先前轨道数据集的轨道间干扰 。

公开(公告)号：US20120063022A1

公开(公告)日：2012-03-15

申请号：US13186174

申请日：2011-07-19

申请人： George Mathew ,  Jongseung Park ,  Shaohua Yang ,  Erich F. Haratsch ,  Ming Jin ,  Yuan Xing Lee

发明人： George Mathew ,  Jongseung Park ,  Shaohua Yang ,  Erich F. Haratsch ,  Ming Jin ,  Yuan Xing Lee

IPC分类号： G11B5/09

CPC分类号： G11B20/10046 ,  G11B5/012 ,  G11B5/09 ,  G11B19/045 ,  G11B20/10398 ,  G11B20/1217 ,  G11B2020/10759 ,  G11B2020/1232 ,  G11B2020/1298 ,  G11B2220/2516

摘要： Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is discussed that includes: a data buffer, an inter-track interference response circuit, and an inter-track interference signal estimator circuit. The data buffer is operable to store a previous track data set. The inter-track interference response circuit is operable to estimate an inter-track interference response from the previous track data set based at least in part on the previous track data set and a current track data set. The inter-track interference signal estimator circuit is operable to calculate an inter-track interference from the previous track data set based at least in part on the previous track data set and the inter-track interference response from the previous track data set.

摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 作为示例，讨论了包括数据缓冲器，轨道间干扰响应电路和轨道间干扰信号估计器电路的数据处理电路。 数据缓冲器可操作以存储先前的轨迹数据集。 轨道间干扰响应电路可用于至少部分地基于先前的轨道数据集和当前轨道数据集来估计来自先前轨道数据集的轨道间干扰响应。 轨道间干扰信号估计器电路可用于至少部分地基于先前的轨道数据集和来自前一轨道数据集的轨道间干扰响应来计算来自先前轨道数据集的轨道间干扰。

公开(公告)号：US08711620B2

公开(公告)日：2014-04-29

申请号：US13588043

申请日：2012-08-17

申请人： Fan Zhang ,  AbdelHakim S. Alhussien ,  Zongwang Li ,  Erich F. Haratsch

发明人： Fan Zhang ,  AbdelHakim S. Alhussien ,  Zongwang Li ,  Erich F. Haratsch

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C7/02 ,  G11C7/1006 ,  G11C16/26 ,  G11C2029/5002

摘要： An apparatus is described that is configured to modify a signal to at least substantially remove a noise portion from the signal. In one or more implementations, the apparatus is a collaborative filtering module that is configured to communicatively couple to a memory array having a plurality of memory cell blocks. The memory array is configured to furnish a signal representative of data stored within the plurality of memory cell blocks. The collaborative filtering module is configured to determine a noise distribution associated with the plurality of memory cell blocks and generate a noise prediction, which is based upon the noise distribution, when a read operation for the plurality of memory cell blocks is issued. The collaborative filtering module is also configured to modify the signal utilizing the noise prediction to at least substantially remove noise from the signal.

摘要翻译： 描述了被配置为修改信号以至少从信号中去除噪声部分的装置。 在一个或多个实现中，该设备是协作过滤模块，其被配置为通信地耦合到具有多个存储器单元块的存储器阵列。 存储器阵列被配置为提供表示存储在多个存储单元块内的数据的信号。 协作过滤模块被配置为当发出多个存储单元块的读取操作时，确定与多个存储器单元块相关联的噪声分布，并产生基于噪声分布的噪声预测。 协同过滤模块还被配置为使用噪声预测来修改信号以至少基本上从信号中去除噪声。

公开(公告)号：US20140078608A1

公开(公告)日：2014-03-20

申请号：US13618317

申请日：2012-09-14

申请人： Jun Xiao ,  Erich F. Haratsch ,  Fan Zhang

发明人： Jun Xiao ,  Erich F. Haratsch ,  Fan Zhang

IPC分类号： G11B5/09

CPC分类号： G11B20/10009 ,  G11B5/012 ,  G11B5/09 ,  G11B20/10046 ,  G11B20/1037 ,  G11B2020/185 ,  G11B2220/2516

摘要： Embodiments of the present inventions are related to systems and methods for data processing, and more particularly to systems and methods for reducing inter-track interference in relation to processing data retrieved from a storage medium.

摘要翻译： 本发明的实施例涉及用于数据处理的系统和方法，更具体地涉及用于减少与从存储介质检索的处理数据相关的轨道间干扰的系统和方法。

公开(公告)号：US20140050023A1

公开(公告)日：2014-02-20

申请号：US13588043

申请日：2012-08-17

申请人： Fan Zhang ,  AbdelHakim S. Alhussien ,  Zongwang Li ,  Erich F. Haratsch

发明人： Fan Zhang ,  AbdelHakim S. Alhussien ,  Zongwang Li ,  Erich F. Haratsch

IPC分类号： G11C7/02 ,  G11C16/26 ,  G11C16/04

CPC分类号： G11C7/02 ,  G11C7/1006 ,  G11C16/26 ,  G11C2029/5002

摘要： An apparatus is described that is configured to modify a signal to at least substantially remove a noise portion from the signal. In one or more implementations, the apparatus is a collaborative filtering module that is configured to communicatively couple to a memory array having a plurality of memory cell blocks. The memory array is configured to furnish a signal representative of data stored within the plurality of memory cell blocks. The collaborative filtering module is configured to determine a noise distribution associated with the plurality of memory cell blocks and generate a noise prediction, which is based upon the noise distribution, when a read operation for the plurality of memory cell blocks is issued. The collaborative filtering module is also configured to modify the signal utilizing the noise prediction to at least substantially remove noise from the signal.

摘要翻译： 描述了被配置为修改信号以至少从信号中去除噪声部分的装置。 在一个或多个实现中，该设备是协作过滤模块，其被配置为通信地耦合到具有多个存储器单元块的存储器阵列。 存储器阵列被配置为提供表示存储在多个存储单元块内的数据的信号。 协作过滤模块被配置为当发出多个存储单元块的读取操作时，确定与多个存储器单元块相关联的噪声分布，并产生基于噪声分布的噪声预测。 协同过滤模块还被配置为使用噪声预测来修改信号以至少基本上从信号中去除噪声。

公开(公告)号：US20130083418A1

公开(公告)日：2013-04-04

申请号：US13460204

申请日：2012-04-30

申请人： Kurt J. Worrell ,  Erich F. Haratsch

发明人： Kurt J. Worrell ,  Erich F. Haratsch

IPC分类号： G11B5/09

CPC分类号： G11B5/09 ,  G11B5/012 ,  G11B19/045

摘要： Hardware-based methods and apparatus are provided for inter-track interference mitigation in magnetic recording systems. Inter-track interference (ITI) cancellation data is stored in a memory of a read channel of a magnetic recording system. The memory can be in a write data path or a read data path of the read channel. The inter-track interference cancellation data is optionally provided to an inter-track interference mitigation circuit using at least a portion of a write data path, for example, based on a control signal. The storage of the inter-track interference cancellation data can be in response to a second control signal.

摘要翻译： 提供基于硬件的方法和装置用于磁记录系统中的轨道间干扰减轻。 轨道间干扰（ITI）抵消数据被存储在磁记录系统的读通道的存储器中。 存储器可以在读取通道的写入数据路径或读取数据路径中。 可以例如基于控制信号，使用写数据路径的至少一部分，将轨道间干扰消除数据任选地提供给轨道间干扰减轻电路。 轨道间干扰消除数据的存储可以响应于第二控制信号。

公开(公告)号：US07971125B2

公开(公告)日：2011-06-28

申请号：US11620988

申请日：2007-01-08

申请人： Nils Graef ,  Erich F. Haratsch

发明人： Nils Graef ,  Erich F. Haratsch

IPC分类号： G11B20/18 ,  H03M13/45

CPC分类号： G11B20/18 ,  H03M13/4146

摘要： Various systems and methods for generating and/or ordering error indications are disclosed herein. In some cases, the error indication is used as an erasure pointer in a memory access system. As one particular example, a system for ordering erasure pointers is disclosed that includes a group of N sort cells, where N is a whole number. Each of the sort cells is operable to maintain a respective error indication that includes an error value and an associated error pointer. Further, the group of N sort cells is operable to receive an incoming error indication including error value and associated error pointer, and to update the error indication of one or more of the group of N sort cells based in part on the incoming error value. The system also includes a selector circuit that is operable to allow selectable access to each of the respective error pointers maintained in the group of N sort cells.

摘要翻译： 本文公开了用于产生和/或排序错误指示的各种系统和方法。 在某些情况下，错误指示用作存储器访问系统中的擦除指针。 作为一个具体示例，公开了一种用于排序擦除指针的系统，其包括一组N个分类单元，其中N是整数。 每个分类单元可操作以维持包括错误值和相关联的错误指针的相应错误指示。 此外，N个分组单元的组可操作以接收包括错误值和相关联的错误指针的输入错误指示，并且部分地基于输入错误值来更新该N个分类单元组中的一个或多个的错误指示。 该系统还包括选择器电路，其可操作以允许对维持在N个分类单元组中的每个相应错误指针的可选择访问。