公开(公告)号：US20060023521A1

公开(公告)日：2006-02-02

申请号：US10710707

申请日：2004-07-29

申请人： John Gabric ,  Harold Pilo

发明人： John Gabric ,  Harold Pilo

IPC分类号： G11C7/00

CPC分类号： G11C7/20 ,  G11C7/12 ,  G11C11/413

摘要： A method for initializing a static random access memory (SRAM) device during power-up includes clamping one of a pair of bitlines of the SRAM device to a logic low potential while allowing the other of the pair of bitlines to be coupled to a charging logic high potential. An SRAM storage cell within the SRAM device is forced to a stable state by selectively allowing a wordline potential of a wordline associated with the SRAM storage cell to follow the charging logic high potential, thereby coupling the SRAM storage cell to the pair of bitlines.

摘要翻译： 用于在上电期间初始化静态随机存取存储器（SRAM）器件的方法包括将SRAM器件的一对位线中的一个钳位到逻辑低电位，同时允许该对位线中的另一个耦合到充电逻辑 高潜力 SRAM器件中的SRAM存储单元通过选择性地允许与SRAM存储单元相关联的字线的字线电位跟随充电逻辑高电位而强制进入稳定状态，从而将SRAM存储单元耦合到该对位线。

公开(公告)号：US20050190640A1

公开(公告)日：2005-09-01

申请号：US10708379

申请日：2004-02-27

申请人： George Braceras ,  Harold Pilo

发明人： George Braceras ,  Harold Pilo

IPC分类号： G11C8/00 ,  G11C11/00 ,  G11C11/413

CPC分类号： G11C11/413

摘要： A method for implementing a self-timed, read to write operation in a memory storage device. In an exemplary embodiment, the method includes capturing a read address during a first half of a current clock cycle, and commencing a read operation so as to read data corresponding to the captured read address onto a pair of bit lines. A write operation is commenced for the current clock cycle so as to cause write data to appear on the pair of bit lines as soon as the read data from the captured read address is amplified by a sense amplifier, wherein the write operation uses a previous write address captured during a preceding clock cycle. A current write address is captured during a second half of the current clock cycle, said current write address used for a write operation implemented during a subsequent clock cycle, wherein the write operation for the current clock cycle is timed independent of the current write address captured during said second half of the current clock cycle.

摘要翻译： 一种用于在存储器存储设备中实现自定时的读写操作的方法。 在一个示例性实施例中，该方法包括在当前时钟周期的前半部分期间捕获读取地址，并开始读取操作，以便将对应于所捕获的读取地址的数据读取到一对位线上。 一旦当前时钟周期开始写入操作，以便一旦来自捕获的读取地址的读取数据被读出放大器放大，就会使写入数据出现在该对位线上，其中写入操作使用先前的写入 在前一个时钟周期捕获的地址。 在当前时钟周期的后半段期间捕获当前写入地址，所述当前写入地址用于在随后的时钟周期期间实现的写入操作，其中当前时钟周期的写入操作被独立于捕获的当前写入地址 在当前时钟周期的后半段。

公开(公告)号：US06915467B2

公开(公告)日：2005-07-05

申请号：US10014032

申请日：2001-12-11

申请人： Harold Pilo

发明人： Harold Pilo

IPC分类号： G11C29/04 ,  G11C29/24 ,  G11C29/34 ,  G11C29/00

CPC分类号： G11C29/24 ,  G11C11/401 ,  G11C2029/2602

摘要： A system and method is disclosed for simultaneously testing columns and column redundancies of a semiconductor memory by temporarily adding an additional parallel signal bit to an input/output data bus associated therewith, the additional parallel signal bit providing greater bandwidth during test mode operation. The input/output data bus has n parallel signal bits which normally carry column data, but the additional parallel signal bit does not normally carry either column data or column redundancy data. The additional parallel signal bit may normally carry a clock signal such as an echo clock associated with the data placed on the data bus.

摘要翻译： 公开了一种系统和方法，用于通过将附加的并行信号位临时添加到与其相关联的输入/输出数据总线来同时测试半导体存储器的列和列冗余，该附加并行信号位在测试模式操作期间提供更大的带宽。 输入/输出数据总线具有通常携带列数据的n个并行信号位，但附加并行信号位通常不携带列数据或列冗余数据。 附加并行信号位通常可以携带时钟信号，例如与放置在数据总线上的数据相关联的回波时钟。

公开(公告)号：US20050007866A1

公开(公告)日：2005-01-13

申请号：US10604184

申请日：2003-06-30

申请人： Darren Anand ,  John Fifield ,  Harold Pilo

发明人： Darren Anand ,  John Fifield ,  Harold Pilo

IPC分类号： G11C29/02 ,  G11C8/00

CPC分类号： G11C29/50012 ,  G11C11/401 ,  G11C29/02 ,  G11C2029/0401 ,  G11C2029/1204

摘要： A method and circuit for timing the start of a precharge period in an eDRAM. The circuit including: a delayed lock loop circuit for receiving a clock signal and generating a control signal for adjusting an internal delay of the clock signal; and means for generating a delayed clock signal in response to the control signal. The means for generating the delayed clock signal is a multiple stage delay circuit, each stage of the multiple delay stage circuit connected in series and each stage individually responsive to the control signal.

摘要翻译： 一种用于定时在eDRAM中预充电期间开始的方法和电路。 该电路包括：延迟锁定环电路，用于接收时钟信号并产生用于调整时钟信号的内部延迟的控制信号; 以及用于响应于控制信号产生延迟的时钟信号的装置。 用于产生延迟时钟信号的装置是多级延迟电路，多级延迟级电路的每级串联连接，每级分别响应控制信号。

公开(公告)号：US06754135B2

公开(公告)日：2004-06-22

申请号：US10065056

申请日：2002-09-13

申请人： Harold Pilo

发明人： Harold Pilo

IPC分类号： G11C700

CPC分类号： G11C7/1012 ,  G11C7/1006 ,  G11C7/103

摘要： A method for bursting data in a wide I/O memory device with improved access time and reduced data-bus complexity. The memory read operation accesses n bits of data which are output in eight n/8-bit I/O words in any particular order in accordance with the burst base address and linear or interleaved burst sequence controls. For every I/O, eight bits of data are presented to a 9-to-1 multiplexer. The first of eight bits in the burst sequence is the access time-limiting bit and is preselected by the burst base addresses of the 9-to-1 multiplexer. Subsequent bits in the burst sequence have extra half-cycles to be output, and use look-aside 8-to-1 multiplexers controlled by a burst counter with timings synchronized to the burst data clock timings.

公开(公告)号：US06208572B1

公开(公告)日：2001-03-27

申请号：US09592055

申请日：2000-06-12

申请人： R. Dean Adams ,  Robert E. Busch ,  Harold Pilo ,  George E. Rudgers

发明人： R. Dean Adams ,  Robert E. Busch ,  Harold Pilo ,  George E. Rudgers

IPC分类号： G11C2900

CPC分类号： G11C29/50

摘要： A semiconductor memory device having resistive bitline contact testing includes memory cells, and wordline logic devices for concurrently activating two adjacent memory cells. The two adjacent memory cells are activated concurrently to allow higher current through a bitline contact for improved detection of resistive bitline contacts. A test cell may also be included to test the integrity of the bitline contact.

摘要翻译： 具有电阻位线接触测试的半导体存储器件包括存储单元和用于同时激活两个相邻存储器单元的字线逻辑器件。 两个相邻的存储单元同时被激活，以允许更高的电流通过位线接点来改善电阻位线触点的检测。 还可以包括测试单元以测试位线接触的完整性。

公开(公告)号：US08654594B2

公开(公告)日：2014-02-18

申请号：US13403252

申请日：2012-02-23

申请人： Igor Arsovski ,  George M. Braceras ,  Harold Pilo

发明人： Igor Arsovski ,  George M. Braceras ,  Harold Pilo

IPC分类号： G11C11/412

CPC分类号： G11C5/147 ,  G11C11/417

摘要： An integrated circuit structure comprises a static random access memory (SRAM) structure and a logic circuit. A power supply is operatively connected to the SRAM structure, and provides a first voltage to the SRAM structure. A voltage limiter is operatively connected to the power supply. The voltage limiter comprises a switching device operatively connected to the power supply. The switching device receives the first voltage and a second voltage supplied to structures external to the SRAM structure. A resistive element is operatively connected to the switching device. The switching device connects the resistive element to the power supply. The resistive element is selected to enable an output from the switching device to the logic circuit when a difference between the first voltage and the second voltage is greater than a voltage threshold value of the switching device.

摘要翻译： 集成电路结构包括静态随机存取存储器（SRAM）结构和逻辑电路。 电源可操作地连接到SRAM结构，并且向SRAM结构提供第一电压。 电压限制器可操作地连接到电源。 电压限制器包括可操作地连接到电源的开关装置。 开关器件接收提供给SRAM结构外部结构的第一电压和第二电压。 电阻元件可操作地连接到开关装置。 开关装置将电阻元件连接到电源。 电阻元件被选择为当第一电压和第二电压之间的差大于开关器件的电压阈值时，使能从开关器件到逻辑电路的输出。

公开(公告)号：US20130135944A1

公开(公告)日：2013-05-30

申请号：US13307245

申请日：2011-11-30

申请人： George M. Braceras ,  Kirk D. Peterson ,  Harold Pilo

发明人： George M. Braceras ,  Kirk D. Peterson ,  Harold Pilo

IPC分类号： G11C5/14

CPC分类号： G11C11/413 ,  G11C5/147 ,  G11C7/12

摘要： Disclosed is a memory array in which the lower of two supply voltages from two power supplies is dynamically selected for bitline pre-charge operations. In the memory array, a voltage comparator compares the first supply voltage on a first power supply rail to a second supply voltage on a second power supply rail and outputs a voltage difference signal. If the voltage difference signal has a first value indicating that the first supply voltage is equal to or less than the second supply voltage, than a control circuit ensures that the complementary bitlines connected to a memory cell are pre-charged to the first supply voltage. If the voltage difference signal has a second value indicating that the first supply voltage is greater than the second supply voltage, then the control circuit ensures that the complementary bitlines are pre-charged to the second supply voltage. Also disclosed is an associated method.

摘要翻译： 公开了一种存储器阵列，其中来自两个电源的两个电源电压中的较低的电源电压被动态地选择用于位线预充电操作。 在存储器阵列中，电压比较器将第一电源轨上的第一电源电压与第二电源轨上的第二电源电压进行比较，并输出电压差信号。 如果电压差信号具有指示第一电源电压等于或小于第二电源电压的第一值，则比控制电路确保连接到存储器单元的互补位线被预充电到第一电源电压。 如果电压差信号具有指示第一电源电压大于第二电源电压的第二值，则控制电路确保互补位线被预充电到第二电源电压。 还公开了相关联的方法。

公开(公告)号：US08437201B2

公开(公告)日：2013-05-07

申请号：US13366804

申请日：2012-02-06

申请人： Igor Arsovski ,  Matthew W. Deming ,  Darryl R. Hill ,  Harold Pilo ,  Reid A. Wistort

发明人： Igor Arsovski ,  Matthew W. Deming ,  Darryl R. Hill ,  Harold Pilo ,  Reid A. Wistort

IPC分类号： G11C8/08

CPC分类号： G11C8/08 ,  G11C11/413

摘要： A dual word-line level shifter circuit and associated SRAM. A circuit is disclosed that includes a first transistor gated by a data input at the lower voltage, and a second transistor gated by a restore input at the higher voltage, wherein the first and second transistors are coupled along a series path to a source at the higher voltage; a control node along the series path; an output node coupled to the control node via a first pair of parallel transistors; and a feedback circuit having a second pair of parallel transistors and a feedback transistor, wherein the feedback transistor couples the second pair of parallel transistors to the control node and is gated by the output node.

摘要翻译： 双字线电平移位电路和相关SRAM。 公开了一种电路，其包括通过较低电压的数据输入门控的第一晶体管和由较高电压的恢复输入门控的第二晶体管，其中第一和第二晶体管沿串联路径耦合到源极 电压较高; 沿着串行路径的控制节点; 输出节点，经由第一对并联晶体管耦合到所述控制节点; 以及具有第二对并联晶体管和反馈晶体管的反馈电路，其中所述反馈晶体管将所述第二对并联晶体管耦合到所述控制节点并由所述输出节点门控。

公开(公告)号：US08279687B2

公开(公告)日：2012-10-02

申请号：US12779608

申请日：2010-05-13

申请人： Chad A. Adams ,  George M. Braceras ,  Daniel M Nelson ,  Harold Pilo ,  Vinod Ramadurai

发明人： Chad A. Adams ,  George M. Braceras ,  Daniel M Nelson ,  Harold Pilo ,  Vinod Ramadurai

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C7/04 ,  G11C11/419

摘要： A reduced bitline precharge level has been found to increase the SRAM Beta ratio, thus improving the stability margin. The precharge level is also supplied to Sense amplifier, write driver, and source voltages for control signals. In the sense amplifier, the lower precharge voltage compensates for performance loss in the bit-cell by operating global data-line drivers with increased overdrive. In the write driver, the reduced voltage improves the Bitline discharge rate, improves the efficiency of the negative boost write assist, and decreases the reliability exposure of transistors in the write path from negative boost circuit.

摘要翻译： 已经发现降低的位线预充电水平增加了SRAM Beta比率，从而提高了稳定裕度。 预充电电平也提供给Sense放大器，写入驱动器和源电压用于控制信号。 在读出放大器中，较低的预充电电压通过以增加的超速驱动来操作全局数据线驱动器来补偿位单元中的性能损失。 在写入驱动器中，降低的电压提高了位线放电速率，提高了负升压写入辅助的效率，并降低了来自负升压电路的写入通路中的晶体管的可靠性暴露。