公开(公告)号：US4961095A

公开(公告)日：1990-10-02

申请号：US314242

申请日：1989-02-22

申请人： Koichiro Mashiko

发明人： Koichiro Mashiko

IPC分类号： H01L27/10 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10829 ,  G11C11/4097 ,  Y10S257/929

摘要： A grooved separating region 112 having information electric charge storing capacitances C.sub.P formed on side surfaces thereof is formed to extend the region between the adjacent word line 107 in parallel with the word line 107. As a result, the grooved separating region 112 does not contact the channel region 111 of the gate transistors and does not intersect the word line 107.

摘要翻译： 形成有形成在其侧表面上的信息电荷存储电容CP的带槽分离区域112，以使得相邻字线107之间的区域与字线107平行地延伸。结果，带槽分隔区域112不接触 沟道区域111，并且不与字线107相交。

公开(公告)号：US4710789A

公开(公告)日：1987-12-01

申请号：US937206

申请日：1986-12-03

申请人： Kiyohiro Furutani ,  Koichiro Mashiko ,  Kazutami Arimoto

发明人： Kiyohiro Furutani ,  Koichiro Mashiko ,  Kazutami Arimoto

IPC分类号： G11C11/401 ,  G11C7/18 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L27/10829 ,  G11C11/4097 ,  G11C7/18

摘要： In a semiconductor memory device, memory cells of a first column each comprising an N-channel FET are connected to a first bit line, and memory cells of a second column each comprising a P-channel FET are connected to a second bit line. The first bit line and the second bit line are connected to complementary terminals of a sense amplifier to form a folded-bit line pair. A work line is connected to the gate of the N-channel FET of one of the memory cells of the first column and to the gate of the P-channel FET of one of the memory cells of the second column. The word line is selectively provided with a first voltage to make conductive the N-channel FET connected thereto and to make nonconductive the P-channel FET connected thereto, or a second voltage to make conductive the P-channel FET connected thereto and to make nonconductive the N-channel FET connected thereto, or a third voltage to make nonconducitve both the N-channel FET and the P-channel FET connected thereto.

摘要翻译： 在半导体存储器件中，包括N沟道FET的第一列的存储单元连接到第一位线，并且包括P沟道FET的第二列的存储单元连接到第二位线。 第一位线和第二位线连接到读出放大器的互补端子以形成折叠位线对。 工作线连接到第一列的存储单元之一的N沟道FET的栅极和第二列的存储单元之一的P沟道FET的栅极。 字线选择性地设置有第一电压，以使与其连接的N沟道FET导通，并使与其连接的P沟道FET不导通，或者使第二电压导通连接到其上的P沟道FET，并使非导通 与其连接的N沟道FET，或第三电压，以使N沟道FET和与其连接的P沟道FET都不导通。

公开(公告)号：US4689770A

公开(公告)日：1987-08-25

申请号：US792071

申请日：1985-10-28

申请人： Hiroshi Miyamoto ,  Koichiro Mashiko ,  Toshifumi Kobayashi ,  Michihiro Yamada

发明人： Hiroshi Miyamoto ,  Koichiro Mashiko ,  Toshifumi Kobayashi ,  Michihiro Yamada

IPC分类号： G11C11/401 ,  G11C5/02 ,  G11C7/18 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C11/24

CPC分类号： G11C5/025 ,  G11C11/4097 ,  G11C7/18 ,  H01L2924/0002

摘要： An LSI semiconductor memory device in which errors in reading out memory cells connected to outermost bit lines of a memory cell array of the device are substantially eliminated. In accordance with the invention, this is done by making capacitances associated with the bit lines of respective ones of the memory cell array substantially equal to one another. To accomplish this, the configuration of an inside portion of wiring other than the bit lines of the array is made the same as that of the bit lines, and the distance between the outermost bit line and the other wiring is made equal to the distance between adjacent ones of the bit lines.

摘要翻译： 基本上消除了读出连接到器件的存储单元阵列的最外位线的存储单元的错误的LSI半导体存储器件。 根据本发明，这是通过使与存储单元阵列中相应的位线相关联的电容基本上彼此相等来实现的。 为了实现这一点，使除阵列的位线之外的布线的内部部分的配置与位线的配置相同，并且使最外侧位线和其它布线之间的距离等于 相邻的位线。

公开(公告)号：US4520466A

公开(公告)日：1985-05-28

申请号：US432385

申请日：1982-09-30

申请人： Koichiro Mashiko

发明人： Koichiro Mashiko

IPC分类号： G11C11/401 ,  G11C11/404 ,  G11C7/00 ,  G11C11/40

CPC分类号： G11C11/404

摘要： A dynamic random access memory comprises a one-transistor type MOS dynamic random access memory of an open bit line type, which comprises two memory arrays at the left and the right sides of sense amplifying circuits (2). Each of both memory arrays comprises a plurality of memory cells (1) and dummy cells (3), each of columns of memory cells (1) and dummy cells (3) having a cell plate voltage control circuit (13) connected at the end thereof through a cell plate (8). Each cell plate voltage control circuit (13) is provided with a control signal .phi..sub.G having a level changing during a period when any of word lines (5) or dummy word lines (6) is selected and is responsive to selection of the word line (5) or the dummy word line (6) to discharge the voltage of the cell plate (8) and is responsive to a change of the level of the control signal .phi..sub.G to charge the cell plate (8). Accordingly, transfer of a signal electric charge from the memory cell (1) and the dummy cell (3) to the bit line (4) is performed at a high speed, and delay of the signal of the word line (5) and the dummy word line (6) is compensated, whereby a high speed operation can be performed. In addition, a signal electric charge stored in the memory cells (1) and the dummy cells (3) is increased and the operation is accordingly stabilized.

摘要翻译： 动态随机存取存储器包括开放位线型的单晶体管型MOS动态随机存取存储器，其包括读出放大电路（2）的左侧和右侧的两个存储器阵列。 两个存储器阵列中的每一个包括多个存储器单元（1）和虚设单元（3），每个存储单元列（1）和虚拟单元（3）具有在端部连接的单元板电压控制电路（13） 通过电池板（8）。 每个单元板电压控制电路（13）具有在选择字线（5）或虚拟字线（6）中的任何一个周期期间具有电平变化的控制信号phi G，并且响应于字线的选择 （5）或虚拟字线（6），以对单元板（8）的电压进行放电，并且响应控制信号phi G的电平的变化来对单元板（8）充电。 因此，以高速度进行从存储单元（1）和虚设单元（3）到位线（4）的信号电荷的传送，并且字线（5）的信号和 伪字线（6）被补偿，从而可以执行高速操作。 此外，存储在存储单元（1）和虚设单元（3）中的信号电荷增加，因此操作稳定。

公开(公告)号：US4333168A

公开(公告)日：1982-06-01

申请号：US176638

申请日：1980-08-08

申请人： Koichiro Mashiko ,  Toshio Ichiyama ,  Makoto Taniguchi

发明人： Koichiro Mashiko ,  Toshio Ichiyama ,  Makoto Taniguchi

IPC分类号： G11C11/409 ,  G11C11/407 ,  G11C11/4099 ,  G11C11/40

CPC分类号： G11C11/4099

摘要： A plurality of single transistor memory cells with electrically charged capacitors and two similar dummy memory cells are electrically coupled in symmetric relationship to a sense amplifier for each row of the disclosed memory circuit. An address signal selects a word line connected to the memory cell on one side of the amplifier and a dummy word line connected to the dummy memory cell on its other side and applies a word signal to the selected word lines, in order to read out electric charges on the capacitors, and the amplifier amplifies a potential difference due to the read charges. For each row two dummy word lines are connected to delay means coupled to the amplifier to form an activating signal for the amplifier by delaying a potential rise developed on the selected dummy word line.

摘要翻译： 具有带电电容器和两个类似的虚拟存储器单元的多个单晶体管存储器单元与所公开的存储器电路的每行的读出放大器对称地电耦合。 地址信号选择连接到放大器一侧的存储单元的字线和连接到另一侧的虚拟存储单元的虚拟字线，并将字信号施加到所选择的字线，以便读出电 对电容器进行充电，并且放大器放大由于读取电荷引起的电位差。 对于每行，两个虚拟字线连接到耦合到放大器的延迟装置，以通过延迟在所选择的虚拟字线上产生的电位上升来形成用于放大器的激活信号。