公开(公告)号：US07859044B2

公开(公告)日：2010-12-28

申请号：US11782079

申请日：2007-07-24

申请人： Robert C. Wong ,  Haining S. Yang

发明人： Robert C. Wong ,  Haining S. Yang

IPC分类号： H01L29/78 ,  H01L27/12

CPC分类号： H01L29/66795 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1211 ,  H01L29/785

摘要： A gate dielectric and a gate conductor layer are formed on sidewalls of at least one semiconductor fin. The gate conductor layer is patterned so that a gate electrode is formed on a first sidewall of a portion of the semiconductor fin, while a second sidewall on the opposite side of the first sidewall is not controlled by the gate electrode. A partially gated finFET, that is, a finFET with a gate electrode on the first sidewall and without a gate electrode on the second sidewall is thus formed. Conventional dual gate finFETs may be formed with the inventive partially gated finFETs on the same substrate to provide multiple finFETs having different on-current in the same circuit such as an SRAM circuit.

摘要翻译： 在至少一个半导体鳍片的侧壁上形成栅极电介质和栅极导体层。 图案化栅极导体层，使得栅极电极形成在半导体鳍片的一部分的第一侧壁上，而在第一侧壁的相对侧上的第二侧壁不受栅电极控制。 因此，形成了部分选通的finFET，即在第一侧壁上具有栅电极且在第二侧壁上没有栅电极的finFET。 传统的双栅极finFET可以在同一衬底上与本发明的部分选通的鳍状FET形成，以在诸如SRAM电路的同一电路中提供具有不同导通电流的多个finFET。

公开(公告)号：US20100295132A1

公开(公告)日：2010-11-25

申请号：US12698302

申请日：2010-02-02

申请人： Ping-Chuan Wang ,  Robert C. Wong ,  Haining S. Yang

发明人： Ping-Chuan Wang ,  Robert C. Wong ,  Haining S. Yang

IPC分类号： H01L27/06 ,  H01L21/8234 ,  H01L21/326

CPC分类号： H01L27/0727 ,  H01L23/5252 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

摘要： Structure and method for providing a programmable anti-fuse in a FET structure. A method of forming the programmable anti-fuse includes: providing a p− substrate with an n+ gate stack; implanting an n+ source region and an n+ drain region in the p− substrate; forming a resist mask over the n+ drain region, while leaving the n+ source region exposed; etching the n+ source region to form a recess in the n+ source region; and growing a p+ epitaxial silicon germanium layer in the recess in the n+ source region to form a pn junction that acts as a programmable diode or anti-fuse.

摘要翻译： 在FET结构中提供可编程反熔丝的结构和方法。 形成可编程反熔丝的方法包括：提供具有n +栅极叠层的p衬底; 在p衬底中注入n +源极区域和n +漏极区域; 在n +漏极区域上形成抗蚀剂掩模，同时使n +源极区域露出; 蚀刻n +源极区域以在n +源极区域中形成凹陷; 以及在n +源极区的凹槽中生长p +外延硅锗层以形成用作可编程二极管或反熔丝的pn结。

公开(公告)号：US20090186476A1

公开(公告)日：2009-07-23

申请号：US12018440

申请日：2008-01-23

申请人： Haining Yang ,  Robert C. Wong

发明人： Haining Yang ,  Robert C. Wong

IPC分类号： H01L21/4763

CPC分类号： H01L27/1104 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1203

摘要： A method of forming an improved static random access memory (SRAM) interconnect structure is provided. The method includes forming a sidewall spacer around a periphery of a patterned poly-silicon layer formed over a silicon layer of a semiconductor substrate; removing the patterned poly-silicon layer for exposing a portion of a cap layer; etching the exposed portion of the cap layer for revealing a portion of the silicon layer; etching the potion of the silicon layer, in which a portion of said silicon layer connects at least a portion of pull-down device of said SRAM to at least a portion of pull-up device of said SRAM; forming a gate oxide; and forming a gate conductor over the gate oxide. An interconnect structure is also provided.

摘要翻译： 提供了形成改进的静态随机存取存储器（SRAM）互连结构的方法。 该方法包括在形成在半导体衬底的硅层上的图案化多晶硅层的周围形成侧壁隔离物; 去除图案化的多晶硅层以暴露盖层的一部分; 蚀刻盖层的暴露部分以露出硅层的一部分; 蚀刻硅层的一部分，其中所述硅层的一部分将所述SRAM的下拉器件的至少一部分连接到所述SRAM的上拉器件的至少一部分; 形成栅极氧化物; 以及在所述栅极氧化物上形成栅极导体。 还提供互连结构。

公开(公告)号：US20090108374A1

公开(公告)日：2009-04-30

申请号：US11928418

申请日：2007-10-30

申请人： Robert C. Wong ,  Haining Sam Yang

发明人： Robert C. Wong ,  Haining Sam Yang

IPC分类号： H01L27/11 ,  H01L21/8244

CPC分类号： H01L27/1104 ,  H01L27/11

摘要： Hybrid SRAM circuit, hybrid SRAM structures and method of fabricating hybrid SRAMs. The SRAM structures include first and second cross-coupled inverters coupled to first and second pass gate devices. The pull-down devices of the inverters are FinFETs while the pull-up devices of the inverters and the pass gate devices are planar FETs or pull-down and pull-up devices of the inverters are FinFETs while the pass gate devices are planar FETs.

摘要翻译： 混合SRAM电路，混合SRAM结构和制造混合SRAM的方法。 SRAM结构包括耦合到第一和第二通道栅极器件的第一和第二交叉耦合反相器。 逆变器的下拉器件是FinFET，而反相器的上拉器件和通栅器件是平面FET，反相器的下拉和上拉器件是FinFET，而栅极器件是平面FET。

公开(公告)号：US20090108287A1

公开(公告)日：2009-04-30

申请号：US11926399

申请日：2007-10-29

申请人： Phung T. Nguyen ,  Robert C. Wong

发明人： Phung T. Nguyen ,  Robert C. Wong

IPC分类号： H01L27/11

CPC分类号： H01L27/11 ,  G11C11/39 ,  H01L29/66659

摘要： A one-transistor static random access memory (1T SRAM) device and circuit implementations are disclosed. The 1T SRAM device includes a planar field effect transistor (FET) on the surface of the cell and a vertical PNPN device integrated to one side of the FET. A base of the PNP of the PNPN device is electrically common to the emitter/collector of the FET and a base of the NPN of the PNPN device is electrically common to the channel region of the FET. The anode pin of the PNPN device may be used as a word line or a bit line. A method of forming the 1T SRAM device is also disclosed.

摘要翻译： 公开了一种单晶体管静态随机存取存储器（1T SRAM）器件和电路实现方式。 1T SRAM器件包括在单元表面上的平面场效应晶体管（FET）和集成在FET一侧的垂直PNPN器件。 PNPN器件的PNP的基极与FET的发射极/集电极电气公共，并且PNPN器件的NPN的基极与FET的沟道区域电气公共。 PNPN器件的阳极引脚可以用作字线或位线。 还公开了一种形成1T SRAM器件的方法。

公开(公告)号：US20090057780A1

公开(公告)日：2009-03-05

申请号：US11845265

申请日：2007-08-27

申请人： Robert C. Wong ,  Haining Yang

发明人： Robert C. Wong ,  Haining Yang

IPC分类号： H01L27/12 ,  H01L21/336 ,  H01L29/76

CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor structure and a method for fabricating the semiconductor structure include a first semiconductor fin and a second semiconductor fin of the same overall height over a substrate. Due to the presence of a channel stop layer at the base of one of the first semiconductor fin and the second semiconductor fin, but not the other of the first semiconductor fin and the second semiconductor fin, the first semiconductor fin and the second semiconductor fin have different channel heights. The semiconductor fins may be used to fabricating a corresponding first finFET and a corresponding second finFET with differing performance characteristics due to the different channel heights of the first semiconductor fin and the second semiconductor fin.

摘要翻译： 半导体结构和制造半导体结构的方法包括在衬底上具有相同整体高度的第一半导体鳍片和第二半导体鳍片。 由于在第一半导体鳍片和第二半导体鳍片之一的基底处存在通道阻挡层而不是第一半导体鳍片和第二半导体鳍片中的另一个，所以第一半导体鳍片和第二半导体鳍片具有 不同渠道高度。 由于第一半导体鳍片和第二半导体鳍片的沟道高度不同，半导体鳍片可以用于制造具有不同性能特性的相应的第一鳍片FET和对应的第二鳍片鳍片。

公开(公告)号：US20090032886A1

公开(公告)日：2009-02-05

申请号：US11830090

申请日：2007-07-30

申请人： Robert C. Wong ,  Haining S. Yang

发明人： Robert C. Wong ,  Haining S. Yang

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L27/088 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0207 ,  Y10S257/903

摘要： A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure which includes a semiconductor substrate. The semiconductor substrate includes (i) a top substrate surface which defines a reference direction perpendicular to the top substrate surface and (ii) first and second semiconductor body regions. The method further includes forming (i) a gate divider region and (ii) a gate electrode layer on top of the semiconductor substrate. The gate divider region is in direct physical contact with gate electrode layer. A top surface of the gate electrode layer and a top surface of the gate divider region are essentially coplanar. The method further includes patterning the gate electrode layer resulting in a first gate electrode region and a second gate electrode region. The gate divider region does not overlap the first and second gate electrode regions in the reference direction.

摘要翻译： 半导体结构及其形成方法。 该方法包括提供包括半导体衬底的半导体结构。 半导体衬底包括（i）限定垂直于顶部衬底表面的参考方向的顶部衬底表面和（ii）第一和第二半导体本体区域。 该方法还包括在半导体衬底的顶部形成（i）栅极分隔区和（ii）栅电极层。 栅极分压器区域与栅极电极层直接物理接触。 栅电极层的顶表面和栅极分隔区的顶表面基本上是共面的。 该方法还包括图案化栅极电极层，形成第一栅电极区域和第二栅电极区域。 栅极分压器区域在参考方向上不与第一和第二栅电极区域重叠。

公开(公告)号：US20080029781A1

公开(公告)日：2008-02-07

申请号：US11427406

申请日：2006-06-29

申请人： Phung T. Nguyen ,  Robert C. Wong

发明人： Phung T. Nguyen ,  Robert C. Wong

IPC分类号： H01L29/74

CPC分类号： H01L29/66659 ,  H01L27/1025 ,  H01L27/1027 ,  H01L27/11

摘要： A one-transistor static random access memory (1T SRAM) device and circuit implementations are disclosed. The 1T SRAM device includes a planar field effect transistor (FET) on the surface of the cell and a vertical PNPN device integrated to one side of the FET. A base of the PNP of the PNPN device is electrically common to the emitter/collector of the FET and a base of the NPN of the PNPN device is electrically common to the channel region of the FET. The anode pin of the PNPN device may be used as a word line or a bit line. A method of forming the 1T SRAM device is also disclosed.

摘要翻译： 公开了一种单晶体管静态随机存取存储器（1T SRAM）器件和电路实现方式。 1T SRAM器件包括在单元表面上的平面场效应晶体管（FET）和集成在FET一侧的垂直PNPN器件。 PNPN器件的PNP的基极与FET的发射极/集电极电气公共，并且PNPN器件的NPN的基极与FET的沟道区域电气公共。 PNPN器件的阳极引脚可以用作字线或位线。 还公开了一种形成1T SRAM器件的方法。

公开(公告)号：US06834003B2

公开(公告)日：2004-12-21

申请号：US10065842

申请日：2002-11-25

申请人： Fred John Towler ,  Robert C. Wong

发明人： Fred John Towler ,  Robert C. Wong

IPC分类号： G11C1500

CPC分类号： G11C15/04

摘要： A Content Addressable Memory (CAM) cell with PFET passgate SRAM cells which results in a smaller cell size because of the more balanced number of 8 PFET devices and 8 NFET devices. The PFET passgates allow the size of the SRAM cell pulldown devices to be reduced, and lower the power dissipation in the SRAM during standby or during read/write.

摘要翻译： 具有PFET通道SRAM单元的内容寻址存储器（CAM）单元，由于8个PFET器件和8个NFET器件的数量更多，导致更小的单元尺寸。 PFET Passgates允许降低SRAM单元下拉器件的尺寸，并在待机或读/写期间降低SRAM中的功耗。

公开(公告)号：US5365117A

公开(公告)日：1994-11-15

申请号：US26653

申请日：1993-03-05

申请人： Robert C. Wong

发明人： Robert C. Wong

IPC分类号： H03K19/013 ,  H03K19/086 ,  H03K19/173 ,  H03K17/00 ,  H03K4/00 ,  H03K12/00

CPC分类号： H03K19/086 ,  H03K19/013 ,  H03K19/1738

摘要： Switchable diffused junction capacitors providing selectable data signal paths in a logic gate. A control circuit, such as a current switch, renders one of the junction capacitors conductive to present a large diffusion capacitance which acts as a fast signal pathway to the respectively applied data signal. Non-conducting junction capacitor presents a negligible diffusion capacitance which essentially acts as an open circuit to the respectively applied data signal. The control circuit response is slow and non-critical. The combination of a slow response control to configure selectable fast response data signal pathways is useful in "half good" or "partial good" semiconductor chip technologies, data buffers with fast flush, and self-test, self-repair chip designs, among others.

摘要翻译： 可切换扩散结电容器在逻辑门中提供可选择的数据信号路径。 诸如电流开关的控制电路使得结电容器中的一个导通以呈现大的扩散电容，其作为到分别施加的数据信号的快速信号路径。 非导电结电容器具有可忽略的扩散电容，其基本上作为分别施加的数据信号的开路。 控制电路响应慢且非关键。 缓慢响应控制配置可选择的快速响应数据信号通路的组合在“半好”或“部分好”半导体芯片技术，具有快速冲洗和自检，自修复芯片设计的数据缓冲器等中是有用的 。