公开(公告)号：US20230239508A1

公开(公告)日：2023-07-27

申请号：US17915431

申请日：2020-12-11

Applicant: Intel Corporation

Inventor： Jill Boyce ,  Basel Salahieh

IPC: H04N19/65 ,  H04N19/597

CPC classification number: H04N19/65 ,  H04N19/597

Abstract: Methods, apparatus, systems and articles of manufacture to identify a video decoding error are disclosed. An example apparatus includes an atlas generator to generate atlas data for one or more atlases generated from input views of video; a hash generator to: perform a hash operation on the atlas data to generate a hash value; and include the hash value in a message; and a multiplexer to combine the one or more atlases, coded atlas data corresponding to the atlas data, and the message to generate a video bitstream.

公开(公告)号：US11663746B2

公开(公告)日：2023-05-30

申请号：US17095544

申请日：2020-11-11

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Prasoonkumar Surti ,  Jill Boyce ,  Subramaniam Maiyuran ,  Michael Apodaca ,  Adam T. Lake ,  James Holland ,  Vasanth Ranganathan ,  Altug Koker ,  Lidong Xu ,  Nikos Kaburlasos

IPC: G06T9/00 ,  G06T15/00 ,  G06N3/045

CPC classification number: G06T9/002 ,  G06N3/045 ,  G06T9/007 ,  G06T9/008 ,  G06T15/005

Abstract: Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides hardware logic to apply a numerical transform to matrix data to increase the sparsity of the data. Increasing the sparsity may result in a higher compression ratio when the matrix data is compressed.

公开(公告)号：US20230007277A1

公开(公告)日：2023-01-05

申请号：US17631298

申请日：2020-09-30

Applicant: INTEL CORPORATION

Inventor： Basel Salahieh ,  Fai Yeung ,  Jill Boyce

IPC: H04N19/169 ,  H04N19/20 ,  H04N19/132

Abstract: Methods, apparatus, systems and articles of manufacture for video coding using object metadata are disclosed. An example apparatus includes an object separator to separate input views into layers associated with respective objects to generate object layers for geometry data and texture data of the input views, a pruner to project the first object layer of a first basic view of the at least one basic views against the first object layer of a first additional view of the at least one additional views to generate a first pruned view and a first pruning mask, a patch packer to tag a patch with an object identifier of the first object, the patch corresponding to the first pruning mask, and an atlas generator to generate at least one atlas to include in encoded video data, the atlas including the patch.

公开(公告)号：US20220174304A1

公开(公告)日：2022-06-02

申请号：US17442056

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Jill Boyce ,  Lidong Xu

IPC: H04N19/46 ,  H04N19/136 ,  H04N19/172 ,  H04N19/167 ,  H04N19/146 ,  H04N19/42

Abstract: Embodiments of a video codec may include technology to derive a conformance point for a sub-region of coded pictures in a coded video sequence in the video data, group any combination of sub-pictures that form a rectangular region into a sub-picture set, and/or derive a level indicator corresponding to a sub-picture based on a level of the coded video sequence and a relative size of the coded picture and the sub-picture set. Other embodiments are disclosed and claimed.

公开(公告)号：US20220159258A1

公开(公告)日：2022-05-19

申请号：US17441211

申请日：2020-06-22

Applicant: INTEL CORPORATION

Inventor： Alexander Alshin ,  Jill Boyce ,  Pavel Frolov ,  Vasily Aristarkhov

IPC: H04N19/13 ,  H04N19/91 ,  H04N19/149 ,  H04N19/184

Abstract: An embodiment of a video codec may include technology to store video data, and utilize a generalized bypass bin to one or more of encode and decode the video data. Other embodiments are disclosed and claimed.

公开(公告)号：US20220109840A1

公开(公告)日：2022-04-07

申请号：US17555092

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Ximin Zhang ,  Zhijun Lei ,  Jill Boyce ,  Sang-Hee Lee

IPC: H04N19/126 ,  H04N19/70 ,  H04N19/423 ,  H04N19/119 ,  H04N19/172 ,  H04N19/18 ,  H04N19/136

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to encode and decode video using quantization matrices. An example apparatus includes interface circuitry to access an input frame of video, quantization matrix syntax encoder circuitry to encode a set of user-defined quantization matrices into a sequence header associated with a sequence of video frames including the input frame, adaptive quantization matrix selector circuitry to select a subset of quantization matrices from a combination of a set of default quantization matrices and the set of user-defined quantization matrices, adaptive segment selector circuitry to select a first one of the subset of quantization matrices for a first segment of the input frame, the input frame to be divided into a plurality of segments including the first segment, and encoder circuitry to quantize transform coefficients of the first segment of the input frame based on the first one of the subset of quantization matrices.

公开(公告)号：US20220086445A1

公开(公告)日：2022-03-17

申请号：US17539099

申请日：2021-11-30

Applicant: Intel Corporation

Inventor： Alexander Alshin ,  Jill Boyce ,  Zhijun Lei ,  Miroslav Goncharenko ,  Vasily Aristarkhov

IPC: H04N19/13 ,  H04N19/91 ,  H04N19/196 ,  H04N19/176

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for multi-symbol equiprobable mode entropy coding. An example apparatus includes equiprobable bypass control circuitry to determine whether an input value associated with the one or more blocks is greater than a reference value. The example apparatus also includes interval control circuitry to, based on the determination, adjust at least one of an upper limit or a lower limit based on an approximate value approximating a product of (1) a quotient of (a) a difference between the alphabet size and one and (b) the alphabet size and (2) the upper limit, the upper limit and the lower limit forming a range of values within which the input value is to be encoded.

公开(公告)号：US11178373B2

公开(公告)日：2021-11-16

申请号：US16050322

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： Mayuresh Varerkar ,  Stanley Baran ,  Michael Apodaca ,  Prasoonkumar Surti ,  Atsuo Kuwahara ,  Narayan Biswal ,  Jill Boyce ,  Yi-Jen Chiu ,  Gokcen Cilingir ,  Barnan Das ,  Atul Divekar ,  Srikanth Potluri ,  Nilesh Shah ,  Archie Sharma

IPC: H04H60/33 ,  H04N13/111 ,  H04N19/597 ,  G06F9/38 ,  G06F3/01 ,  G06N20/00

Abstract: A mechanism is described for facilitating adaptive resolution and viewpoint-prediction for immersive media in computing environments. An apparatus of embodiments, as described herein, includes one or more processors to receive viewing positions associated with a user with respect to a display, and analyze relevance of media contents based on the viewing positions, where the media content includes immersive videos of scenes captured by one or more cameras. The one or more processors are further to predict portions of the media contents as relevant portions based on the viewing positions and transmit the relevant portions to be rendered and displayed.

公开(公告)号：US11057631B2

公开(公告)日：2021-07-06

申请号：US16596204

申请日：2019-10-08

Applicant: Intel Corporation

Inventor： Jill Boyce

IPC: H04N19/196 ,  H04N19/70 ,  H04N19/463 ,  H04N19/42 ,  H04N19/136

Abstract: A mechanism is described for facilitating defining of interoperability signaling and conformance points for the PCC standard in computing environments. A computing device of embodiments, as described herein, includes a decoder to decode a compressed bitstream of video data representing a point cloud, point cloud reconstructor circuitry to reconstruct a point cloud from the decoded patch video data, a syntax element parser to receive at least one syntax element representing interoperability signaling in the compressed bitstream to indicate the number of points in one or more pictures of the video data, and processing hardware to determine if the number of points in the one or more pictures of the compressed bitstream is within the conformance limits of the point cloud reconstructor circuitry.

公开(公告)号：US10951903B2

公开(公告)日：2021-03-16

申请号：US16235574

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Palanivel Guruva Reddiar ,  Jill Boyce

IPC: H04N19/179 ,  G06F16/783 ,  H04N19/169 ,  H04N19/136 ,  H04N21/44 ,  H04N21/643 ,  H04N21/218 ,  H04N21/84 ,  H04N21/2187 ,  H04N19/70

Abstract: Embodiments are generally directed to video analytics encoding for improved efficiency of video processing and compression. An embodiment of an apparatus includes a memory to store data, including data for video streaming, and a video processing mechanism, wherein the video processing mechanism is to analyze video data and generate video analytics, generate metadata representing the video analytics and insert the generated video analytics metadata into a message, and transmit the video data and the metadata to a succeeding apparatus or system in a video analytics pipeline, the video data being compressed video data.