公开(公告)号：US10985903B2

公开(公告)日：2021-04-20

申请号：US16158659

申请日：2018-10-12

Applicant: Intel Corporation

Inventor： Raghavan Kumar ,  Sanu K. Mathew ,  Sudhir K. Satpathy ,  Vikram B. Suresh

IPC: H04L29/06 ,  H04L9/00 ,  H04L9/06

Abstract: A processing system includes a processing core and a hardware accelerator communicatively coupled to the processing core. The hardware accelerator includes a random number generator to generate a byte order indicator. The hardware accelerator also includes a first switching module communicatively coupled to the random value indicator generator. The switching module receives an byte sequence in an encryption round of the cryptographic operation and feeds a portion of the input byte sequence to one of a first substitute box (S-box) module or a second S-box module in view of a byte order indicator value generated by the random number generator.

公开(公告)号：US10884957B2

公开(公告)日：2021-01-05

申请号：US16160952

申请日：2018-10-15

Applicant: Intel Corporation

Inventor： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor W. Lee ,  Abhishek Sharma ,  Huseyin E. Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young

IPC: G06F13/16 ,  G06F13/28 ,  G06N20/00

Abstract: Techniques and mechanisms for performing in-memory computations with circuitry having a pipeline architecture. In an embodiment, various stages of a pipeline each include a respective input interface and a respective output interface, distinct from said input interface, to couple to different respective circuitry. These stages each further include a respective array of memory cells and circuitry to perform operations based on data stored by said array. A result of one such in-memory computation may be communicated from one pipeline stage to a respective next pipeline stage for use in further in-memory computations. Control circuitry, interconnect circuitry, configuration circuitry or other logic of the pipeline precludes operation of the pipeline as a monolithic, general-purpose memory device. In other embodiments, stages of the pipeline each provide a different respective layer of a neural network.

公开(公告)号：US10748603B2

公开(公告)日：2020-08-18

申请号：US16146473

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Knag ,  Abhishek Sharma ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Ram Krishnamurthy ,  Ian A. Young

IPC: G11C8/00 ,  G11C11/418 ,  G06F9/30 ,  G11C11/419 ,  G11C13/00 ,  G11C7/10 ,  G11C11/54 ,  G06N3/063 ,  G06N3/08 ,  G11C7/18 ,  G06F7/544 ,  G11C11/16

Abstract: A memory circuit has compute-in-memory circuitry that enables a multiply-accumulate (MAC) operation based on shared charge. Row access circuitry drives multiple rows of a memory array to multiply a first data word with a second data word stored in the memory array. The row access circuitry drives the multiple rows based on the bit pattern of the first data word. Column access circuitry drives a column of the memory array when the rows are driven. Accessed rows discharge the column line in an accumulative fashion. Sensing circuitry can sense voltage on the column line. A processor in the memory circuit computes a MAC value based on the voltage sensed on the column.

公开(公告)号：US10713558B2

公开(公告)日：2020-07-14

申请号：US15395231

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram K. Krishnamurthy

IPC: G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: In one embodiment, a method comprises determining that a membrane potential of a first neuron of a first neuron core exceeds a threshold; determining a first plurality of synapse cores that each store at least one synapse weight associated with the first neuron; and sending a spike message to the determined first plurality of synapse cores.

公开(公告)号：US20190319796A1

公开(公告)日：2019-10-17

申请号：US16456034

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： SANTOSH GHOSH ,  Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Andrew H. Reinders ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L9/32 ,  H04L9/08 ,  H04L9/30 ,  H04L9/06

Abstract: In one example an apparatus comprises a computer readable memory, an XMSS verification manager logic to manage XMSS verification functions, a one-time signature and public key generator logic, a chain function logic to implement chain function algorithms, a low latency SHA3 hardware engine, and a register bank communicatively coupled to the XMSS verification manager logic. Other examples may be described.

公开(公告)号：US20190116023A1

公开(公告)日：2019-04-18

申请号：US16158659

申请日：2018-10-12

Applicant: Intel Corporation

Inventor： Raghavan Kumar ,  Sanu K. Mathew ,  Sudhir K. Satpathy ,  Vikram B. Suresh

IPC: H04L9/00 ,  H04L9/06

Abstract: A processing system includes a processing core and a hardware accelerator communicatively coupled to the processing core. The hardware accelerator includes a random number generator to generate a byte order indicator. The hardware accelerator also includes a first switching module communicatively coupled to the random value indicator generator. The switching module receives an byte sequence in an encryption round of the cryptographic operation and feeds a portion of the input byte sequence to one of a first substitute box (S-box) module or a second S-box module in view of a byte order indicator value generated by the random number generator.

公开(公告)号：US10256973B2

公开(公告)日：2019-04-09

申请号：US15283000

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Raghavan Kumar ,  Sanu K. Mathew ,  Avinash L. Varna ,  Vikram B. Suresh ,  Sudhir K. Satpathy

IPC: H04L9/06 ,  H03K19/21 ,  H04L9/00 ,  G09C1/00 ,  G11C19/00

Abstract: Described is an apparatus comprising an S-box circuitry operable to convert a value on an input into a value on an output in accordance with an Advanced Encryption Standard (AES) Rijndael S-box matrix. The apparatus also comprises a pseudo-random number generation (PRG) circuitry operable to provide a sequence of pseudo-random numbers on a first output and a registered copy of the sequence on a second output. The apparatus further comprises a mask circuitry operable to provide an XOR of a value on the output of the S box circuitry and a value on the first output of the PRG circuitry. The apparatus additionally comprises a mask removal circuitry operable to provide an XOR of a value on an output of the data register circuitry, a value coupled to an output of a key register circuitry, and a value on the second output of the PRG circuitry.

公开(公告)号：US20190102669A1

公开(公告)日：2019-04-04

申请号：US15721653

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Kshitij Bhardwaj ,  Raghavan Kumar ,  Huseyin E. Sumbul ,  Phil Knag ,  Ram K. Krishnamurthy ,  Himanshu Kaul

IPC: G06N3/04 ,  G06N3/063

Abstract: In one embodiment, a processor comprises a first neuromorphic core to implement a plurality of neural units of a neural network, the first neuromorphic core comprising a memory to store a current time-step of the first neuromorphic core; and a controller to track current time-steps of neighboring neuromorphic cores that receive spikes from or provide spikes to the first neuromorphic core; and control the current time-step of the first neuromorphic core based on the current time-steps of the neighboring neuromorphic cores.

公开(公告)号：US20180189631A1

公开(公告)日：2018-07-05

申请号：US15395231

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram K. Krishnamurthy

IPC: G06N3/04 ,  G06N3/08

CPC classification number: G06N3/04 ,  G06N3/049 ,  G06N3/063 ,  G06N3/08

Abstract: In one embodiment, a method comprises determining that a membrane potential of a first neuron of a first neuron core exceeds a threshold; determining a first plurality of synapse cores that each store at least one synapse weight associated with the first neuron; and sending a spike message to the determined first plurality of synapse cores.

公开(公告)号：US20170288855A1

公开(公告)日：2017-10-05

申请号：US15088823

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Raghavan Kumar ,  Sanu K. Mathew ,  Sudhir K. Satpathy ,  Vikram B. Suresh

IPC: H04L9/00 ,  G06F7/58 ,  H04L9/06

CPC classification number: H04L9/003 ,  H04L9/0631 ,  H04L9/0637 ,  H04L9/0662 ,  H04L2209/046 ,  H04L2209/125 ,  H04L2209/24

Abstract: A processing system includes a processing core and a hardware accelerator communicatively coupled to the processing core. The hardware accelerator includes a random number generator to generate a byte order indicator. The hardware accelerator also includes a first switching module communicatively coupled to the random value indicator generator. The switching module receives an byte sequence in an encryption round of the cryptographic operation and feeds a portion of the input byte sequence to one of a first substitute box (S-box) module or a second S-box module in view of a byte order indicator value generated by the random number generator.