公开(公告)号：US10733690B2

公开(公告)日：2020-08-04

申请号：US15982693

申请日：2018-05-17

Applicant: Intel Corporation

Inventor： John Gierach ,  Abhishek Venkatesh ,  Travis Schluessler ,  Devan Burke ,  Tomer Bar-On ,  Michael Apodaca

IPC: G06T1/20 ,  G06T17/10

Abstract: Embodiments are generally directed to GPU mixed primitive topology type processing. An embodiment of an apparatus includes one or more processor cores; and a memory to store data for graphics processing, wherein the one or more processing cores are to generate in the memory a vertex buffer to store vertex data for a mesh to be rendered and an index buffer to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for multiple primitive topology types. The one or more processor cores are to process the index data for the plurality of primitive topology types from the index buffer and fetch vertex data from the vertex buffer; and are to set up each primitive topology type of the plurality of primitive topology types for processing in a single draw operation.

公开(公告)号：US20190355084A1

公开(公告)日：2019-11-21

申请号：US15982693

申请日：2018-05-17

Applicant: Intel Corporation

Inventor： John Gierach ,  Abhishek Venkatesh ,  Travis Schluessler ,  Devan Burke ,  Tomer Bar-On ,  Michael Apodaca

IPC: G06T1/20 ,  G06T17/10

Abstract: Embodiments are generally directed to GPU mixed primitive topology type processing. An embodiment of an apparatus includes one or more processor cores; and a memory to store data for graphics processing, wherein the one or more processing cores are to generate in the memory a vertex buffer to store vertex data for a mesh to be rendered and an index buffer to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for multiple primitive topology types. The one or more processor cores are to process the index data for the plurality of primitive topology types from the index buffer and fetch vertex data from the vertex buffer; and are to set up each primitive topology type of the plurality of primitive topology types for processing in a single draw operation.

公开(公告)号：US10452552B2

公开(公告)日：2019-10-22

申请号：US15488988

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Andrew T. Lauritzen ,  Gabor Liktor ,  Tomer Bar-On ,  Hugues Labbe ,  John G. Gierach ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  Balaji Vembu ,  Altug Koker

IPC: G06F12/0862 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/0811 ,  G06F12/0855 ,  G06F9/38 ,  G06T1/20

Abstract: Systems, apparatuses and methods may provide a way to track graphics pipeline operations. More particularly, the systems, apparatuses and methods may provide a way to track operation dependencies between graphics pipeline operations for blocks of pixel samples and stall one or more of the pipeline operations based on the operation dependencies. The systems, apparatuses and methods may further provide cache pre-fetch hardware to monitor processing of blocks of pixel samples and fetch a next block of the pixel samples from the memory into a cache before completion of processing a current block of pixel samples based on one or more of the pipeline operations or a surface state of one or more regions of a screen space.

公开(公告)号：US10372416B2

公开(公告)日：2019-08-06

申请号：US15499893

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Yaniv Fais ,  Tomer Bar-On ,  Jacob Subag ,  Jeremie Dreyfuss ,  Lev Faivishevsky ,  Michael Behar ,  Amit Bleiweiss ,  Guy Jacob ,  Gal Leibovich ,  Itamar Ben-Ari ,  Galina Ryvchin ,  Eyal Yaacoby

IPC: G06F7/533 ,  G06N20/00 ,  G06T1/20

Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190147640A1

公开(公告)日：2019-05-16

申请号：US16173722

申请日：2018-10-29

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Atsuo Kuwahara ,  Hugues Labbe ,  Sameer KP ,  Jonathan Kennedy ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Tomer Bar-On ,  Carsten Benthin ,  Adam T. Lake ,  Vasanth Ranganathan ,  Abhishek R. Appu

IPC: G06T15/08 ,  H04N5/369 ,  G06T15/00 ,  G06T15/60 ,  G06T15/10 ,  H04N5/232 ,  H04N13/239 ,  H04N13/344 ,  G06K9/00 ,  G02B27/01

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.

公开(公告)号：US20180314934A1

公开(公告)日：2018-11-01

申请号：US15499900

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Eran Ben-Avi ,  Neta Zmora ,  Guy Jacob ,  Lev Faivishevsky ,  Jeremie Dreyfuss ,  Tomer Bar-On ,  Jacob Subag ,  Yaniv Fais ,  Shira Hirsh ,  Orly Weisel ,  Zigi Walter ,  Yarden Oren

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/063

Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180314899A1

公开(公告)日：2018-11-01

申请号：US15499889

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Jeremie Dreyfuss ,  Amit Bleiweiss ,  Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag ,  Eran Ben-Avi ,  Neta Zmora ,  Tomer Schwartz

IPC: G06K9/00 ,  G06N3/08 ,  G06N3/04 ,  G06K9/62

Abstract: In an example, an apparatus comprises logic, at least partially including hardware logic, to save one or more outputs of a deep learning neural network in a storage system of an autonomous vehicle and upload the one or more outputs to a remote server. Other embodiments are also disclosed and claimed.

公开(公告)号：US20250053797A1

公开(公告)日：2025-02-13

申请号：US18812822

申请日：2024-08-22

Applicant: Intel Corporation

Inventor： Amit Bleiweiss ,  Abhishek Venkatesh ,  Gokce Keskin ,  John Gierach ,  Oguz Elibol ,  Tomer Bar-On ,  Huma Abidi ,  Devan Burke ,  Jaikrishnan Menon ,  Eriko Nurvitadhi ,  Pruthvi Gowda Thorehosur Appajigowda ,  Travis T. Schluessler ,  Dhawal Srivastava ,  Nishant Patel ,  Anil Thomas

IPC: G06N3/063 ,  G06F9/38 ,  G06N3/04 ,  G06N3/08 ,  G06N5/046 ,  G06N20/00 ,  G06T1/20

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a at least one processor to perform operations to implement a neural network and compute logic to accelerate neural network computations.

公开(公告)号：US12086705B2

公开(公告)日：2024-09-10

申请号：US15858014

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Amit Bleiweiss ,  Abhishek Venkatesh ,  Gokce Keskin ,  John Gierach ,  Oguz Elibol ,  Tomer Bar-On ,  Huma Abidi ,  Devan Burke ,  Jaikrishnan Menon ,  Eriko Nurvitadhi ,  Pruthvi Gowda Thorehosur Appajigowda ,  Travis T. Schluessler ,  Dhawal Srivastava ,  Nishant Patel ,  Anil Thomas

IPC: G06N3/063 ,  G06F9/38 ,  G06N3/04 ,  G06N3/08 ,  G06N5/046 ,  G06N20/00 ,  G06T1/20

CPC classification number: G06N3/063 ,  G06F9/3887 ,  G06N3/04 ,  G06N3/08 ,  G06N5/046 ,  G06N20/00 ,  G06T1/20

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a at least one processor to perform operations to implement a neural network and compute logic to accelerate neural network computations.

公开(公告)号：US12033063B2

公开(公告)日：2024-07-09

申请号：US18174275

申请日：2023-02-24

Applicant: Intel Corporation

Inventor： Eran Ben-Avi ,  Neta Zmora ,  Guy Jacob ,  Lev Faivishevsky ,  Jeremie Dreyfuss ,  Tomer Bar-On ,  Jacob Subag ,  Yaniv Fais ,  Shira Hirsch ,  Orly Weisel ,  Zigi Walter ,  Yarden Oren

IPC: G06N3/06 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084

CPC classification number: G06N3/063 ,  G06N3/044 ,  G06N3/045 ,  G06N3/084

Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.