公开(公告)号：US07091769B2

公开(公告)日：2006-08-15

申请号：US10626766

申请日：2003-07-25

Applicant: Myeong Ju Kwon ,  Jae Jin Lee

Inventor： Myeong Ju Kwon ,  Jae Jin Lee

IPC: G05F1/10

CPC classification number: H02M3/073 ,  H02M2003/077

Abstract: A voltage generator with reduced noise features a detector, a controller, a sub-booster, a main booster and a voltage adder. The detector receives an output voltage, a first reference voltage and a second reference voltage lower than the first reference voltage, and then outputs a first sensing signal and a second sensing signal. The controller receives the first sensing signal and the second sensing signal and an action signal to output a first control signal and a second control signal. The sub-booster boosts a voltage in response of the first control signal. The main booster boosts a voltage in response to the second control signal. The voltage adder adds output signals from the sub-booster and main booster, to provide the output voltage.

Abstract translation: 具有降低噪声的电压发生器具有检测器，控制器，副升压器，主升压器和电压加法器。 检测器接收输出电压，第一参考电压和低于第一参考电压的第二参考电压，然后输出第一感测信号和第二感测信号。 控制器接收第一感测信号和第二感测信号以及动作信号，以输出第一控制信号和第二控制信号。 副升压器响应于第一控制信号而升高电压。 主增压器响应于第二控制信号而升高电压。 电压加法器将来自副升压器和主升压器的输出信号相加，以提供输出电压。

公开(公告)号：US06873192B2

公开(公告)日：2005-03-29

申请号：US10608529

申请日：2003-06-30

Applicant: Chang Seok Kang ,  Jae Jin Lee

Inventor： Chang Seok Kang ,  Jae Jin Lee

IPC: G11C5/14 ,  H03K17/22 ,  H03L7/00

CPC classification number: H03K17/223

Abstract: A power-up detection apparatus comprises a voltage divider, a potential detector and a buffer. The voltage divider divides an inputted power voltage in a predetermined ratio. The potential detector compares a predetermined potential with a potential outputted from said voltage divider, and outputs the comparison result. The buffer changes the level of said comparison result when said comparison result outputted from said potential detector is maintained at a predetermined potential for a predetermined period. As a result, a semiconductor device can be stably initialized because a power-up signal is generated only when an externally inputted power voltage is maintained at a current state over a predetermined period although the state of the external power voltage is toggled by noise.

Abstract translation: 上电检测装置包括分压器，电位检测器和缓冲器。 分压器以预定的比例分压输入的电源电压。 电位检测器将预定电位与从所述分压器输出的电位进行比较，并输出比较结果。 当从所述电位检测器输出的所述比较结果在预定时间段内保持预定电位时，所述缓冲器改变所述比较结果的电平。 结果，半导体器件可以被稳定地初始化，因为只有当外部输入的电源电压在预定时间段内保持在当前状态时才产生上电信号，尽管外部电源电压的状态被噪声转换。

公开(公告)号：US06731560B2

公开(公告)日：2004-05-04

申请号：US10313445

申请日：2002-12-06

Applicant: Seok Cheol Yoon ,  Jae Jin Lee ,  Sang Hee Kang ,  Chul Ho Kim

Inventor： Seok Cheol Yoon ,  Jae Jin Lee ,  Sang Hee Kang ,  Chul Ho Kim

IPC: G11C700

CPC classification number: G11C29/783 ,  G11C11/406 ,  G11C11/4085 ,  G11C11/4087 ,  G11C29/24 ,  G11C2029/1202 ,  G11C2029/1802

Abstract: A refresh apparatus for a semiconductor memory device and a refresh method thereof that can reduce a test time by simultaneously refreshing a normal cell and a redundant cell in one test mode is disclosed. The refresh apparatus for the semiconductor memory device may include a redundant cell refresh signal generator for generating a redundant cell refresh signal for refreshing a redundant cell when a refresh is requested in a test mode, a wordline enable signal generator for generating a normal main wordline enable signal and a redundant main wordline enable signal in response to the redundant cell refresh signal in a redundant cell test mode and a wordline driver for simultaneously refreshing the normal and redundant cells by simultaneously driving a normal main wordline and a redundant main wordline in response to the redundant cell refresh signal, the normal main wordline enable signal, the redundant main wordline enable signal and a row address in the redundant cell test mode.

Abstract translation: 公开了一种用于半导体存储器件的刷新装置及其刷新方法，其可以通过在一个测试模式中同时刷新正常单元和冗余单元来减少测试时间。 半导体存储器件的刷新装置可以包括冗余单元刷新信号发生器，用于在测试模式下请求刷新时产生用于刷新冗余单元的冗余单元刷新信号;字线使能信号发生器，用于产生正常主字线使能 信号和冗余主字线使能信号，以响应于冗余单元测试模式中的冗余单元刷新信号和字线驱动器，用于通过同时驱动正常主字线和冗余主字线来同时刷新正常冗余单元和冗余单元，以响应于 冗余单元刷新信号，正常主字线使能信号，冗余主字线使能信号和冗余单元测试模式中的行地址。

公开(公告)号：US06661735B2

公开(公告)日：2003-12-09

申请号：US10025100

申请日：2001-12-18

Applicant: Jae Jin Lee

Inventor： Jae Jin Lee

IPC: G11C800

CPC classification number: G11C7/225 ,  G11C7/22 ,  G11C29/14 ,  G11C29/48

Abstract: An improved semiconductor memory device able to detect problems that appear in a high-speed circuit operation is disclosed. The device may include a data input/output operation by making an internal clock signal be a high frequency signal synchronized with an external clock signal at its rising and falling edges, which results in performing a high-speed test operation in a wafer level.

公开(公告)号：US06473145B1

公开(公告)日：2002-10-29

申请号：US09656371

申请日：2000-09-06

Applicant: Hwan Soo Shim ,  Dong Hae Seo ,  Jae Jin Lee ,  Sang Un Choi

Inventor： Hwan Soo Shim ,  Dong Hae Seo ,  Jae Jin Lee ,  Sang Un Choi

IPC: G02F1136

CPC classification number: G02F1/133553 ,  G02F1/133305 ,  G02F1/133512 ,  G02F1/134363 ,  G02F2001/133334

Abstract: The present invention discloses a reflective plate having lightweight functioning as a substrate and a reflective LCD using the same. The reflective LCD according to the present invention comprises: a transparent insulating substrate; a gate bus line and a data bus line formed at an inner side of the substrate and defining a pixel region; a pixel electrode formed in the pixel region; a switching device operating the pixel electrode by receiving the signals of the gate bus line and the data bus line; a black matrix formed on the surface of the substrate 1s and covering a portion at which the gate bus line, the data bus line, and the switching device are formed; color filters respectively formed at the outsides of the black matrix; and a plastic reflective plate opposing to the inner side of the substrate, wherein the plastic reflective plate comprises: a plastic plate; a photoresist layer disposed on the plastic plate and having an uneven portion on the surface thereof; a reflective film having a high reflectance coated on the photoresist layer having the uneven portion; a planarization layer formed on the photoresist layer so as to planarize the surface of the photoresist layer; a transparent electrode disposed over the planarization layer; and an alignment layer formed over the transparent electrode.

Abstract translation: 本发明公开了一种具有轻质功能的基板的反射板和使用该反射板的反射型LCD。 根据本发明的反射型LCD包括：透明绝缘基板; 栅极总线和数据总线，形成在衬底的内侧并限定像素区域; 形成在所述像素区域中的像素电极; 开关装置，通过接收栅极总线和数据总线的信号来操作像素电极; 形成在基板1s的表面上并覆盖形成栅极总线，数据总线和开关装置的部分的黑色矩阵; 分别形成在黑色矩阵的外侧的滤色器; 以及与所述基板的内侧相对的塑料反射板，其中所述塑料反射板包括：塑料板; 光致抗蚀剂层，其设置在塑料板上并且在其表面上具有不平坦部分; 具有高反射率的反射膜涂覆在具有不平坦部分的光致抗蚀剂层上; 平坦化层，形成在光致抗蚀剂层上，以平坦化光致抗蚀剂层的表面; 设置在所述平坦化层上的透明电极; 以及形成在透明电极上的取向层。

公开(公告)号：US06356494B2

公开(公告)日：2002-03-12

申请号：US09751455

申请日：2001-01-02

Applicant: Ji Eun Jang ,  Mi Young Kim ,  Jae Jin Lee

Inventor： Ji Eun Jang ,  Mi Young Kim ,  Jae Jin Lee

IPC: G11C700

CPC classification number: G11C7/109 ,  G11C7/1078

Abstract: The present invention discloses an automatic precharge apparatus of a semiconductor memory device. An object of the present invention is to perform a sable precharge operation unrelated to change of the clock frequency by controlling to perform an precharge operation after constant delay time, regardless of an external clock signal. The automatic precharge apparatus of a semiconductor memory device comprises an automatic precharge signal generating unit receiving external control signals and then generating an internal precharge command signal, and outputting an automatic precharge signal by using the internal precharge command signal and control signals being related to a bust operation, a ras precharge signal generating unit for generating a ras precharge signal by receiving the automatic precharge signal, a delay unit for outputting a write recovery signal with a constant delay time, which is disabled in the reading operation and only enabled in the writing operation, when an internal precharge command signal is inputted, a ras generating unit for generating a ras signal without a delay time when inputting an external precharge command signal, whereas after a constant delay time in response to the write recovery signal when inputting the ras precharge signal.

Abstract translation: 本发明公开了一种半导体存储装置的自动预充电装置。 本发明的目的是通过控制在恒定的延迟时间之后执行预充电操作，而不管外部时钟信号如何，执行与时钟频率变化无关的可切换预充电操作。 半导体存储器件的自动预充电装置包括自动预充电信号发生单元，其接收外部控制信号，然后产生内部预充电命令信号，并且通过使用内部预充电命令信号和与胸部相关的控制信号输出自动预充电信号 ras预充电信号产生单元，用于通过接收自动预充电信号产生ras预充电信号;延迟单元，用于输出具有恒定延迟时间的写恢复信号，该读恢复信号在读操作中被禁止，并且仅在写操作中有效 当输入内部预充电命令信号时，在输入外部预充电命令信号时产生ras信号而没有延迟时间的ras产生单元，而在输入ras预充电信号时响应于写恢复信号的恒定延迟时间 。

公开(公告)号：US06211700B1

公开(公告)日：2001-04-03

申请号：US09342068

申请日：1999-06-29

Applicant: Jae Jin Lee

Inventor： Jae Jin Lee

IPC: H03K19096

CPC classification number: H03K19/0966 ,  G11C7/1048

Abstract: A data transfer device having a post charge logic circuit which utilizes signals on a pair of data lines performs a post charge operation on the other a plurality of data line pairs. A data transfer device uses only signals on a pair of data lines to perform the post charge operation to the other data lines, thereby reducing the area of the memory device.

Abstract translation: 具有使用一对数据线上的信号的后置充电逻辑电路的数据传送装置在多个数据线对上进行后充电操作。 数据传送装置仅使用一对数据线上的信号对其他数据线执行后充电操作，从而减小存储装置的面积。

公开(公告)号：US5989961A

公开(公告)日：1999-11-23

申请号：US116904

申请日：1998-07-17

Applicant: Jeon Wook Yang ,  Jae Kyoung Mun ,  Eung Gie Oh ,  Jae Jin Lee ,  Kwang Eui Pyun

Inventor： Jeon Wook Yang ,  Jae Kyoung Mun ,  Eung Gie Oh ,  Jae Jin Lee ,  Kwang Eui Pyun

IPC: H01L29/78 ,  H01L21/338 ,  H01L29/812 ,  H01L21/336

CPC classification number: H01L29/66856 ,  H01L29/812

Abstract: Disclosed is a method for manufacturing a vertical channel transistor comprising the steps of: selectively implanting a dopant of high concentration into a semiconductor substrate to form a source region; firstly etching the semiconductor substrate using an insulator and a first photoresist pattern as a mask; secondly etching the substrate using a second photoresist pattern having a shape corresponding to said source region as a mask; implanting a dopant of low concentration into the exposed substrate using said second photoresist pattern as a mask to form a vertical channel layer; implanting a dopant of high concentration into the exposed substrate using same mask to form a drain region; activating said dopants, and forming an ohmic contact layer on said drain region; thirdly etching using a third photoresist pattern for exposing the firstly etched portion of the substrate as a mask; depositing a gate metal on the substrate exposed by the thirdly etching; and wiring a metal, respectively. This invention can be easily manufactured a vertical channel transistor having a low parasitic resistance and an extremely small gate length without sophicated complex processes.

Abstract translation: 公开了用于制造垂直沟道晶体管的方法，包括以下步骤：选择性地将高浓度的掺杂剂注入到半导体衬底中以形成源极区; 首先使用绝缘体和第一光致抗蚀剂图案作为掩模蚀刻半导体衬底; 其次使用具有对应于所述源区域的形状的第二光致抗蚀剂图案作为掩模蚀刻所述基板; 使用所述第二光致抗蚀剂图案作为掩模将低浓度的掺杂剂注入暴露的衬底中以形成垂直沟道层; 使用相同的掩模将高浓度的掺杂剂注入暴露的衬底中以形成漏区; 激活所述掺杂剂，并在所述漏极区上形成欧姆接触层; 第三次使用第三光致抗蚀剂图案进行蚀刻，以将基板的第一蚀刻部分暴露为掩模; 在通过第三次蚀刻暴露的衬底上沉积栅极金属; 并分别接线金属。 本发明可以容易地制造具有低寄生电阻和非常小的栅极长度的垂直沟道晶体管，而无需复杂的复杂工艺。

公开(公告)号：US5854769A

公开(公告)日：1998-12-29

申请号：US944708

申请日：1997-10-06

Applicant: Jae Jin Lee

Inventor： Jae Jin Lee

IPC: G11C8/06 ,  G11C8/00

CPC classification number: G11C8/06

Abstract: An address input buffer for a semiconductor memory device comprising an address buffering circuit fox buffering at least two external address signals A1 and A2, at least two output terminals for outputting the external address signals A1 and A2 buffered by the address buffering circuit as internal address signals AI.sub.-- 1 and AI.sub.-- 2, respectively, a multiplexing circuit connected between the address buffering circuit and the output terminals, for selectively transferring the external address signals A1 and A2 buffered by the address buffering circuit to the output terminals, and a multiplexing control circuit for controlling the multiplexing circuit. According to the present invention, the address input buffer for the semiconductor memory device can convert the external address signals in such a manner that memory cells in the memory device can fairly be accessed.

Abstract translation: 一种用于半导体存储器件的地址输入缓冲器，包括缓冲至少两个外部地址信号A1和A2的地址缓冲电路狐，至少两个输出端，用于输出由地址缓冲电路缓存的外部地址信号A1和A2作为内部地址信号 AI-1和AI-2分别连接在地址缓冲电路和输出端之间的多路复用电路，用于将由地址缓冲电路缓存的外部地址信号A1和A2选择性地传送到输出端，以及复用控制电路 用于控制复用电路。 根据本发明，用于半导体存储器件的地址输入缓冲器可以以可以公平地访问存储器件中的存储单元的方式转换外部地址信号。

公开(公告)号：US5805928A

公开(公告)日：1998-09-08

申请号：US670842

申请日：1996-06-28

Applicant: Jae Jin Lee

Inventor： Jae Jin Lee

IPC: G11C11/407 ,  G11C7/10 ,  G06F13/28

CPC classification number: G11C7/1021

Abstract: A burst length detection circuit comprising at least two registers, each the registers storing a corresponding one of at least two external address signals therein, at least two internal address signal generators, each of the internal address signal generators inputting a corresponding one of the at least two external address signals as its initial value and sequentially incrementing it by one in response to a clock signal to sequentially generate internal address signals, at least two comparators, each of the comparators being operated in response to a control signal to compare an output signal from a corresponding one of the at least two internal address signal generators with an output signal from a corresponding one of the at least two registers, a logic circuit for performing a logic operation with respect to output signals from at least two comparators to detect a burst end time point, and a burst signal generation circuit for generating a burst mode signal with a desired logic value in response to an external burst command signal and a burst end signal from the logic circuit.

Abstract translation: 一种突发长度检测电路，包括至少两个寄存器，每个寄存器存储其中至少两个外部地址信号中的相应一个，至少两个内部地址信号发生器，每个内部地址信号发生器输入至少一个对应的一个 两个外部地址信号作为其初始值，并且响应于时钟信号顺序地增加一个，以顺序地产生内部地址信号，至少两个比较器，每个比较器响应于控制信号而被操作，以比较来自 所述至少两个内部地址信号发生器中的对应的一个内部地址信号发生器具有来自所述至少两个寄存器中对应的一个寄存器的输出信号;逻辑电路，用于相对于来自至少两个比较器的输出信号执行逻辑运算以检测突发结束 时间点和用于产生具有期望逻辑v的脉冲串模式信号的脉冲信号发生电路 响应于来自逻辑电路的外部脉冲串命令信号和突发结束信号。