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112 条记录 (耗时 0.031 秒)

    Method and apparatus for processing frame classification information between network processors
    61.
    发明授权
    Method and apparatus for processing frame classification information between network processors 失效
    用于处理网络处理器之间帧分类信息的方法和装置

    公开(公告)号：US07106730B1

    公开(公告)日：2006-09-12

    申请号：US09546833

    申请日：2000-04-11

    申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    IPC分类号： H04L12/56

    CPC分类号： H04L49/30

    摘要： A network device including an ingress processor and egress processor which receives frames of data over the network on an input port, and transfers it to an appropriate output port. The received frame is processed by an ingress processor which prepares an intra-switch frame for delivery to an egress processor serving a relevant output port of the switch. The intra-switch frame includes a frame header having parameters which have been determined by the ingress processor, as well as data indicating an address for the egress processor for beginning processing of the frame. By identifying to the egress processor processing which has already taken place, the egress processor is relieved of any redundant processing of the frame. The egress processor provides a hardware frame classifier which decodes the information contained in the intra-frame header to derive parameters which have been previously computed as well as a starting address for the egress processor. By reducing the amount of redundant processing of the egress processor, total device throughput delay is reduced.

    摘要翻译： 一种网络设备，包括入口处理器和出口处理器，其在输入端口上通过网络接收数据帧，并将其传送到适当的输出端口。 接收到的帧由入口处理器处理，入口处理器准备一个内部交换帧，用于传送到服务于交换机的相关输出端口的出口处理器。 帧内切换帧包括具有由入口处理器确定的参数的帧报头，以及指示用于开始处理该帧的出口处理器的地址的数据。 通过识别已经发生的出口处理器处理，出口处理器免除了帧的任何冗余处理。 出口处理器提供硬件帧分类器，其对包含在帧内报头中的信息进行解码以导出先前已经计算的参数以及出口处理器的起始地址。 通过减少出口处理器的冗余处理量，减少了总设备吞吐量延迟。

    Stateless message processing scheme for network processors interactions
    62.
    发明授权
    Stateless message processing scheme for network processors interactions 失效

    公开(公告)号：US07085850B2

    公开(公告)日：2006-08-01

    申请号：US09934886

    申请日：2001-08-22

    申请人： Jean Louis Calvignac ,  Mohammad Peyravian ,  Fabrice Jean Verplanken

    发明人： Jean Louis Calvignac ,  Mohammad Peyravian ,  Fabrice Jean Verplanken

    IPC分类号： G06F15/16

    CPC分类号： H04L29/06 ,  H04L69/22

    摘要： A stateless message-passing scheme for interactions between a network processor and a coprocessor is provided. The network processor, when receiving data frames for transmission from a network element to another network element encapsulates the entire packet that it receives within a frame. In this frame, there is provided a header field and a data field. The data field contains the data that needs to be transferred, and the header field contains all of the information regarding the deep-processing that the coprocessor is to perform so that no information of any type need be stored either by the network processor or separately regarding the processing of the data in the data packet. The coprocessor performs the operation designated by the header and returns the altered packet and header to the network processor.

    Method and system for network processor scheduling outputs based on multiple calendars
    64.
    发明授权
    Method and system for network processor scheduling outputs based on multiple calendars 失效
    基于多个日历的网络处理器调度输出的方法和系统

    公开(公告)号：US06862292B1

    公开(公告)日：2005-03-01

    申请号：US09548910

    申请日：2000-04-13

    申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    IPC分类号： H04L12/56 ,  H04Q11/04 ,  H04L12/28

    CPC分类号： H04Q11/0478 ,  H04L47/2425 ,  H04L47/50 ,  H04L47/52 ,  H04L47/627 ,  H04L2012/5636 ,  H04L2012/5649 ,  H04L2012/5651 ,  H04L2012/5679 ,  H04L2012/5681

    摘要： A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. The priorities in the preferred embodiment include a low latency service, a minimum bandwidth, a weighted fair queueing and a system for preventing a user from continuing to exceed his service levels over an extended period. The present invention includes a plurality of calendars with different service rates to allow a user to select the service rate which he desires. If a customer has chosen a high bandwidth for service, the customer will be included in a calendar which is serviced more often than if the customer has chosen a lower bandwidth.

    摘要翻译： 一种将信息单元从网络处理器移动到数据传输网络的系统和方法，其以容纳几个不同级别的服务的优先顺序排列。 本发明包括一种方法和系统，用于根据存储的与信息单元的各种源相关联的优先级来调度来自网络处理单元的处理的信息单元（或帧）的出口。 优选实施例中的优先级包括低延迟服务，最小带宽，加权公平排队以及用于在较长时间内防止用户继续超过其服务水平的系统。 本发明包括具有不同服务速率的多个日历，以允许用户选择他所期望的服务速率。 如果客户选择了高带宽的服务，客户将被包含在比客户选择较低带宽的情况下更频繁地服务的日历。

    Hybrid search memory for network processor and computer systems
    68.
    发明授权
    Hybrid search memory for network processor and computer systems 有权
    用于网络处理器和计算机系统的混合搜索存储器

    公开(公告)号：US08195705B2

    公开(公告)日：2012-06-05

    申请号：US10015165

    申请日：2001-12-11

    申请人： Jean Louis Calvignac ,  Fabrice Jean Verplanken

    发明人： Jean Louis Calvignac ,  Fabrice Jean Verplanken

    IPC分类号： G06F17/30

    CPC分类号： G06F17/30327

    摘要： A system includes a data structure having a Direct Table (DT), Patricia-Trees, Pointers and high speed storage systems such as Contents Address Memory (CAM). The DT has a plurality of entries with each one coupled to a Patricia Tree having multiple nodes coupled to leaves. The number of Nodes, termed a threshold, that can be traversed to obtain information in the leaves is limited to a predetermined value. Once the threshold is reached a pointer indicates the address of the CAM and the address of the leaves is stored in the CAM. By using the structure and method the latency associated with tree search is significantly reduced.

    摘要翻译： 系统包括具有直接表（DT），帕特里夏树，指针和诸如内容地址存储器（CAM）的高速存储系统的数据结构。 DT具有多个条目，其中每个条目耦合到具有耦合到叶子的多个节点的Patricia Tree。 被称为阈值的节点数量，可以被遍历以获得叶子中的信息被限制到预定值。 一旦达到阈值，指针指示CAM的地址，并且叶子的地址被存储在CAM中。 通过使用结构和方法，与树搜索相关联的延迟显着降低。