公开(公告)号：US08018341B2

公开(公告)日：2011-09-13

申请号：US11919497

申请日：2006-05-17

申请人： Tomoaki Atsumi ,  Yutaka Shionoiri ,  Hidetomo Kobayashi

发明人： Tomoaki Atsumi ,  Yutaka Shionoiri ,  Hidetomo Kobayashi

IPC分类号： G08B13/14

CPC分类号： G06K19/07749 ,  G06K19/0708

摘要： Initialization of a semiconductor device can be efficiently performed, which transmits and receives data through wireless communication. The semiconductor device includes an antenna, a power source circuit, a circuit which uses a DC voltage generated by the power source circuit as a power source voltage, and a resistor. The antenna includes a pair of terminals and receives a wireless signal (a modulated carrier wave). The power source circuit includes a first terminal and a second terminal and generates a DC voltage between the first terminal and the second terminal by using a received wireless signal (the modulated carrier wave). The resistor is connected between the first terminal and the second terminal. In this manner, the semiconductor device and the wireless communication system can transmit and receive data accurately.

摘要翻译： 可以有效地执行半导体器件的初始化，其通过无线通信发送和接收数据。 半导体器件包括天线，电源电路，使用由电源电路产生的直流电压作为电源电压的电路和电阻器。 天线包括一对终端，并接收无线信号（调制载波）。 电源电路包括第一端子和第二端子，并且通过使用接收的无线信号（调制载波）在第一端子和第二端子之间产生直流电压。 电阻器连接在第一端子和第二端子之间。 以这种方式，半导体器件和无线通信系统可以准确地发送和接收数据。

公开(公告)号：US08006217B2

公开(公告)日：2011-08-23

申请号：US12562837

申请日：2009-09-18

申请人： Tomoaki Atsumi

发明人： Tomoaki Atsumi

IPC分类号： G06F17/50

CPC分类号： H03K23/52 ,  Y10T29/41

摘要： To reduce current consumption in a frequency-division circuit, particularly in a multistage frequency-division circuit, in a multistage frequency-division circuit, an inputted signal has a higher frequency in a preceding stage, and an inputted signal has a lower frequency in a following stage. Thus, placement is performed preferentially from the basic cell corresponding to the frequency-division circuit into which a signal having a higher frequency is inputted, and then wiring connection is performed. In other words, the layout of a plurality of basic cells corresponding to a multistage frequency-division circuit is performed so that, as compared to a wiring into which a signal having a lower frequency is inputted, a wiring into which a signal having a higher frequency is inputted has a shorter wiring length and has less intersection with other wirings, so that parasitic capacitance and parasitic resistance of the wiring are reduced.

摘要翻译： 为了减少多级分频电路中的分频电路，特别是在多级分频电路中的电流消耗，输入信号在前级具有较高的频率，并且输入信号在 后续阶段 因此，优选地从对应于输入了具有较高频率的信号的分频电路的基本单元进行布置，然后进行布线连接。 换句话说，执行与多级分频电路相对应的多个基本单元的布局，使得与输入具有较低频率的信号的布线相比，具有较高频率的信号的布线 频率输入具有较短的布线长度，并且与其它布线的交点较少，因此布线的寄生电容和寄生电阻降低。

公开(公告)号：US20110079650A1

公开(公告)日：2011-04-07

申请号：US12894719

申请日：2010-09-30

申请人： Hidetomo Kobayashi ,  Tomoaki Atsumi ,  Seiichi Yoneda ,  Yasuyuki Takahashi ,  Kiyoshi Kato

发明人： Hidetomo Kobayashi ,  Tomoaki Atsumi ,  Seiichi Yoneda ,  Yasuyuki Takahashi ,  Kiyoshi Kato

IPC分类号： G06K19/073 ,  G11C7/00

CPC分类号： G06K19/07 ,  G06K19/0701 ,  G11C5/142

摘要： A semiconductor device includes a memory portion, a logic portion, and a plurality of signal lines for electrically connecting the memory portion and the logic portion. In the case where a transfer rate between the semiconductor device and a communication device is α [bps], a first clock frequency generated in the logic portion is Kα [Hz] (K is an integer of 1 or more), the number of reading signal lines of the plurality of signal lines is n (n is an integer of 2 or more), and a second clock frequency generated in the logic portion is Lα/n [Hz] (L is any integer satisfying L/n

摘要翻译： 半导体器件包括用于电连接存储器部分和逻辑部分的存储器部分，逻辑部分和多条信号线。 在半导体器件和通信器件之间的传输速率为α[bps]的情况下，在逻辑部分中产生的第一时钟频率为Kα[Hz]（K为1以上的整数），读取次数 多条信号线的信号线为n（n为2以上的整数），在逻辑部分生成的第二时钟频率为Lα/ n [Hz]（L为满足L / n

公开(公告)号：US07877068B2

公开(公告)日：2011-01-25

申请号：US12003354

申请日：2007-12-21

申请人： Tomoaki Atsumi ,  Hidetomo Kobayashi

发明人： Tomoaki Atsumi ,  Hidetomo Kobayashi

IPC分类号： H04B1/16

CPC分类号： G06K19/0723 ,  G06K19/0702 ,  G06K19/07786 ,  H04B5/0062

摘要： A demodulation signal is generated by provision of a demodulation signal generation circuit to the semiconductor device capable of wireless communication and by obtainment of a difference between voltages having opposite polarities by the demodulation signal generation circuit. Alternatively, a plurality of demodulation signal generation circuits and a selective circuit which selects a demodulation signal generation circuit depending on characteristics of a received signal are provided, where operation of a second demodulation signal generation circuit stops when a first demodulation signal generation circuit is operated. The selective circuit includes an inverter circuit, a flip-flop circuit, and a selector circuit. When the second demodulation signal generation circuit has a comparator and the like, power consumption thereof is reduced.

摘要翻译： 通过向能够进行无线通信的半导体装置提供解调信号生成电路，并且通过解调信号生成电路获得具有相反极性的电压之间的差异来生成解调信号。 或者，提供多个解调信号生成电路和根据接收信号的特性来选择解调信号生成电路的选择电路，其中当第一解调信号产生电路被操作时第二解调信号产生电路的操作停止。 选择电路包括反相器电路，触发器电路和选择器电路。 当第二解调信号发生电路具有比较器等时，其功耗降低。

公开(公告)号：US20100258811A1

公开(公告)日：2010-10-14

申请号：US12822260

申请日：2010-06-24

申请人： Satoshi Murakami ,  Yosuke Tsukamoto ,  Tomoaki Atsumi ,  Masayuki Sakakura

发明人： Satoshi Murakami ,  Yosuke Tsukamoto ,  Tomoaki Atsumi ,  Masayuki Sakakura

IPC分类号： H01L27/12

CPC分类号： H01L29/04 ,  G02F1/13454 ,  G02F1/136204 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124

摘要： In manufacturing a semiconductor device, static electricity is generated while contact holes are formed in an interlayer insulating film by dry etching. Damage to a pixel region or a driving circuit region due to travel of the static electricity generated is prevented. Gate signal lines are spaced apart from each other above a crystalline semiconductor film. Therefore a first protective circuit is not electrically connected when contact holes are opened in an interlayer insulating film. The static electricity generated during dry etching for opening the contact holes moves from the gate signal line, damages a gate insulating film, passes the crystalline semiconductor film, and again damages the gate insulating film before it reaches the gate signal line. As the static electricity generated during the dry etching damages the first protective circuit, the energy of the static electricity is reduced until it loses the capacity of damaging a driving circuit TFT. The driving circuit TFT is thus prevented from suffering electrostatic discharge damage.

摘要翻译： 在制造半导体器件时，通过干蚀刻在层间绝缘膜中形成接触孔时产生静电。 防止了由于所产生的静电的行进而对像素区域或驱动电路区域的损害。 栅极信号线在结晶半导体膜之上彼此间隔开。 因此，当在层间绝缘膜中打开接触孔时，第一保护电路不电连接。 在干蚀刻期间产生的用于打开接触孔的静电从栅极信号线移动，损坏栅极绝缘膜，通过晶体半导体膜，并且在栅极绝缘膜到达栅极信号线之前再次损坏栅极绝缘膜。 由于在干蚀刻期间产生的静电损害第一保护电路，所以静电的能量减小，直到损失驱动电路TFT的能力。 从而防止了驱动电路TFT遭受静电放电损坏。

公开(公告)号：US20100205519A1

公开(公告)日：2010-08-12

申请号：US12768217

申请日：2010-04-27

申请人： Masafumi ITO ,  Tomoaki Atsumi

发明人： Masafumi ITO ,  Tomoaki Atsumi

IPC分类号： H03M13/09 ,  G06F12/02 ,  G06F11/10

CPC分类号： H03M13/09 ,  H04B1/10

摘要： An object of the present invention is to provide a CRC circuit with more simple structure and low power consumption. The CRC circuit includes a first shift register to a p-th shift register, a first EXOR to a (p−1)th EXOR, and a switching circuit. A data signal, a select signal, and an output of a last stage of the p-th shift register are inputted to the switching circuit, and the switching circuit switches a first signal or a second signal in response to the select signal to be outputted.

摘要翻译： 本发明的目的是提供一种具有更简单的结构和低功耗的CRC电路。 CRC电路包括到第p移位寄存器的第一移位寄存器，第一EXOR到第（p-1）个EXOR和开关电路。 数据信号，选择信号和第p移位寄存器的最后级的输出被输入到开关电路，并且开关电路响应于要输出的选择信号而切换第一信号或第二信号 。

公开(公告)号：US07704812B2

公开(公告)日：2010-04-27

申请号：US11607021

申请日：2006-12-01

申请人： Kiyoshi Kato ,  Tomoaki Atsumi ,  Atsuo Isobe

发明人： Kiyoshi Kato ,  Tomoaki Atsumi ,  Atsuo Isobe

IPC分类号： H01L21/00

CPC分类号： H01L21/02678 ,  H01L21/02683 ,  H01L21/2026 ,  H01L27/12 ,  H01L27/1281 ,  H01L29/66757 ,  H01L29/78675 ,  H01L29/78696

摘要： According to the invention, a plurality of semiconductor devices which are required to have conformance are formed from crystalline semiconductor films having uniform crystallinity on the same line, and a semiconductor circuit in which variation between semiconductor devices is small can be provided, and a semiconductor integrated circuit having high conformance can be provided. The invention is characterized in that, in a part or whole of thin film transistors which configure an analog circuit such as a current mirror circuit, a differential amplifier circuit, or an operational amplifier, in which high conformance is required for semiconductor devices included therein, channel forming regions have crystalline semiconductor films on the same line. High conformance can be expected for an analog circuit which has the crystalline semiconductor films on the same line formed using the invention as the channel forming regions of the thin film transistors. That is, the invention is characterized in that, among the thin film transistors which configures the analog circuit, the channel forming regions of the thin film transistors having at least the same polarity are formed on the same line.

摘要翻译： 根据本发明，需要具有一致性的多个半导体器件由同一直线上具有均匀结晶度的晶体半导体膜形成，并且可以提供其中半导体器件之间的变化小的半导体电路，以及半导体集成 可以提供具有高一致性的电路。 本发明的特征在于，在其中包括其中的半导体器件需要高一致性的诸如电流镜电路，差分放大器电路或运算放大器的模拟电路的一部分或全部中， 通道形成区域在同一行上具有结晶半导体膜。 对于具有使用本发明形成的同一线上的晶体半导体膜作为薄膜晶体管的沟道形成区域的模拟电路，可以期待高度一致性。 也就是说，本发明的特征在于，在构成模拟电路的薄膜晶体管中，在同一线上形成具有至少相同极性的薄膜晶体管的沟道形成区域。

公开(公告)号：US20090255995A1

公开(公告)日：2009-10-15

申请号：US11921557

申请日：2006-06-21

申请人： Yutaka Shionoiri ,  Tomoaki Atsumi

发明人： Yutaka Shionoiri ,  Tomoaki Atsumi

IPC分类号： G06K19/06

CPC分类号： H01L27/1266 ,  G06K19/0701 ,  G06K19/0715 ,  G06K19/0723 ,  H01L27/1214 ,  H01L27/13

摘要： Among transistors used in an analog circuit portion of the semiconductor device, particularly in a high frequency circuit, a power supply circuit, and a data demodulation circuit, and transistors used in a digital circuit portion (logic circuit portion), a gate length of a transistor in the analog circuit portion is not less than a gate length of a transistor in the digital circuit portion. As a result, when an excess voltage is supplied, voltage in the analog circuit with a long gate length is suppressed to prevent the damage of elements such as transistors in the digital circuit portion to which a signal is inputted from the analog circuit.

摘要翻译： 在半导体器件的模拟电路部分中使用的晶体管中，特别是在高频电路，电源电路和数据解调电路中使用的晶体管以及在数字电路部分（逻辑电路部分）中使用的晶体管的栅极长度 模拟电路部分中的晶体管不小于数字电路部分中的晶体管的栅极长度。 结果，当提供过电压时，抑制长栅极长度的模拟电路中的电压，以防止从模拟电路输入信号的数字电路部分中的晶体管等元件的损坏。

公开(公告)号：US07332815B2

公开(公告)日：2008-02-19

申请号：US11005963

申请日：2004-12-07

申请人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

发明人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

IPC分类号： G03C1/85

CPC分类号： H01L27/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention has an object to provide a semiconductor device, an ID tag, in which delay of signal transmission with conductive layers is controlled. In addition, the other object is that a design method of such a semiconductor device is provided.A semiconductor device of the invention comprises a plurality of conductive layers, a plurality of first element groups each of which selects one among the conductive layers and a plurality of second element groups each of which amplifies a signal each transmitted from the conductive layers. Each of the second element groups is disposed between the first element groups. Stated another way, the first element group and the second element group are disposed alternately. The delay of the signal transmission with the plurality of conductive layers is controlled because a load by a parasitic capacitance is reduced due to the above feature.

摘要翻译： 本发明的目的是提供一种其中控制有导电层的信号​​传输延迟的半导体器件，ID标签。 此外，另一个目的是提供这种半导体器件的设计方法。 本发明的半导体器件包括多个导电层，多个第一元件组，每个第一元件组中的每一个选择导电层中的一个，以及多个第二元件组，每个第二元件组放大每个从导电层传输的信号。 每个第二元件组设置在第一元件组之间。 换句话说，第一元件组和第二元件组交替布置。 由于上述特征，由于寄生电容的负载减小，因此控制与多个导电层的信号​​传输的延迟。

公开(公告)号：US20070290207A1

公开(公告)日：2007-12-20

申请号：US11802458

申请日：2007-05-23

申请人： Tomoaki Atsumi ,  Hiroki Inoue

发明人： Tomoaki Atsumi ,  Hiroki Inoue

IPC分类号： H01L29/94 ,  H01L21/20

CPC分类号： H01L21/02683 ,  H01L21/02532 ,  H01L21/2026 ,  H01L27/1255 ,  H01L27/1285 ,  H01L27/1296 ,  H01L28/40

摘要： In a semiconductor device including a digital circuit portion and an analog circuit portion having a capacitor portion provided over a substrate, the capacitor portion is provided with a first wiring, a second wiring and a plurality of blocks each having a plurality of capacitor elements. Further, each the plurality of capacitor elements provided in each block has a semiconductor film having a first impurity region and a plurality of second impurity regions provided apart with the first impurity region interposed therebetween, and a conductive film provided over the first impurity region with an insulating film therebetween. A capacitor is formed from the first impurity region, the insulating film, and the conductive film.

摘要翻译： 在包括数字电路部分和具有设置在基板上的电容器部分的模拟电路部分的半导体器件中，电容器部分设置有第一布线，第二布线和多个具有多个电容器元件的块。 此外，设置在每个块中的多个电容器元件中的每一个具有半导体膜，该半导体膜具有第一杂质区和设置有分隔开第一杂质区的多个第二杂质区，并且在第一杂质区上设置有导电膜， 绝缘膜。 由第一杂质区，绝缘膜和导电膜形成电容器。