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公开(公告)号：US4589941A
公开(公告)日：1986-05-20
申请号：US696631
申请日：1985-01-30
申请人： Toshihiro Tanaka , Keiichi Yoshimi , Shigeo Goto
发明人： Toshihiro Tanaka , Keiichi Yoshimi , Shigeo Goto
IPC分类号： F16G1/28 , B29C43/22 , B29C70/08 , B29C70/46 , B29D29/08 , B29K21/00 , B29K105/10 , B29K105/24 , B32B31/06
CPC分类号： B29C70/083 , B29C43/222 , B29C43/228 , B29C70/462 , B29D29/085 , B29C2059/027
摘要： A method of forming a double timing belt wherein a belt preform is firstly formed with teeth on one face thereof. The opposite face of the belt in which the tensile cord is embedded is provided with oppositely projecting teeth in accurate alignment with the teeth of the preform by a successive molding of pluralities of such teeth to the opposite face, with the preform entrained about a pair of adjustably spaced toothed pulleys. Accurate uniform pitch line difference is maintained by providing shims between the mold and belt support during the molding of the second set of teeth to the preform. The mold and support are retained in accurate alignment by cooperating dowels and recesses on the support and mold members. Cooling devices are provided at opposite ends of the mold for preventing full vulcanization of the tooth rubber thereat.
摘要翻译： 一种形成双重同步皮带的方法，其中带状预成型件首先在其一个表面上形成有齿。 其中嵌入有拉伸绳的带的相对面设置有相反突出的齿，其通过将多个这种齿连续模制成相对的面而与预成型体的齿准确对准，预成型件夹带在一对 可调节间隔的带齿皮带轮。 在将第二组牙齿模制到预成型件期间，通过在模具和带支撑件之间提供垫片来保持精确的均匀节距线差异。 模具和支撑件通过在支撑件和模具构件上配合榫钉和凹槽保持准确对准。 冷却装置设置在模具的相对两端，用于防止在其上完全硫化牙齿橡胶。
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公开(公告)号：US08597787B2
公开(公告)日：2013-12-03
申请号：US12517594
申请日：2007-12-13
IPC分类号： B32B27/02
CPC分类号： D01F1/10 , C08G18/0828 , C08G18/2865 , C08G18/4854 , C08G18/542 , C08G18/6453 , C08G18/6674 , C08G18/6685 , C08L75/04 , D01F6/70 , D01F6/94 , Y10T428/29 , Y10T428/2967 , Y10T442/413 , Y10T442/602
摘要： Disclosed is a polyurethane elastic yarn which is excellent in elongation, resilience, heat resistance, alkali resistance, chemical resistance, and capability of being dyed with a cationic dye and which is suitable for use in a stretch cloth, a wearing apparel or the like. The polyurethane elastic yarn comprises: an elastic yarn comprising a polyurethane mainly composed of a polymer diol and a diisocyanate; and a polymer of a compound having a sulfonate group contained in the elastic yarn.
摘要翻译： 公开了伸长性，回弹性，耐热性，耐碱性，耐化学性和用阳离子染料染色的能力优异的聚氨酯弹性丝，适用于弹力布，服装等。 聚氨酯弹性纱线包括：弹性纱线，其包含主要由聚合物二醇和二异氰酸酯组成的聚氨酯; 以及弹性纱中含有磺酸酯基的化合物的聚合物。
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公开(公告)号：US20120296016A1
公开(公告)日：2012-11-22
申请号：US13515949
申请日：2010-12-16
申请人： Toshihiro Tanaka , Masashi Hara
发明人： Toshihiro Tanaka , Masashi Hara
IPC分类号： C08L75/04 , C08K5/3475
摘要： ProblemTo provide a polyurethane elastic yarn with excellent elongation, recoverability, and light resistance that is suitable for use in stretchable fabrics and clothing, and to provide a method for manufacture thereof.Resolution MeansInclude a benzotriazole ultraviolet absorber containing one or more unsaturated bond in the molecule when manufacturing elastic yarn made of polyurethane with a polymeric diol and diisocyanate as starting material.
摘要翻译： 问题提供一种适用于伸缩性织物和衣物的优异伸长率，可回复性和耐光性的聚氨酯弹性丝，并提供其制造方法。 分解方法当制备由聚氨酯制成的弹性纱线和二异氰酸酯作为原料时，在分子中含有一个含有一个或多个不饱和键的苯并三唑紫外线吸收剂。
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公开(公告)号：US08309510B2
公开(公告)日：2012-11-13
申请号：US12601214
申请日：2008-07-09
IPC分类号： C11D1/80
CPC分类号： C11D1/29 , A61K8/86 , A61Q5/02 , A61Q19/10 , B01F17/0057 , C07C303/24 , C07C305/10
摘要： The invention relates to a surfactant composition containing an alkyl ether sulfate represented by the following formula (1): RO—(PO)m(EO)nSO3M (1) wherein R represents a linear alkyl group having 8 to 24 carbon atoms, PO and EO represent a propyleneoxy group and an ethyleneoxy group, respectively, m and n denote the average numbers of added moles of PO and EO, respectively, and are numbers meeting: 0
摘要翻译： 本发明涉及含有下式（1）表示的烷基醚硫酸盐的表面活性剂组合物：RO-（PO）m（EO）nSO3M（1）其中R表示碳原子数为8〜24的直链烷基，PO和 EO分别表示丙烯氧基和亚乙基氧基，m和n分别表示PO和EO的平均加成摩尔数，分别满足：0
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公开(公告)号：US08130571B2
公开(公告)日：2012-03-06
申请号：US13162180
申请日：2011-06-16
申请人： Yutaka Shinagawa , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
发明人： Yutaka Shinagawa , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
IPC分类号： G11C7/00
CPC分类号： G11C16/349 , G11C16/06 , G11C16/3495
摘要： A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed In an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior In a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more.
摘要翻译： 半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写非易失性存储区域。 非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。 第一非易失性存储区具有用于存储大于第二非易失性存储区的信息的阈值电压的最大变化宽度。 当用于存储信息的阈值电压的最大变化幅度较大时，由于由于存储信息的重写操作而对存储单元的应力变大，所以不利于保证重写操作的次数; 然而，由于读取电流变大，因此可以加快存储器信息的读取速度。 可以优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以对第二非易失性存储器区域进行优先排列以保证存储器信息的重写操作的次数更多。
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公开(公告)号：US08050085B2
公开(公告)日：2011-11-01
申请号：US10521553
申请日：2002-08-29
申请人： Masatoshi Takahashi , Takanori Yamazoe , Kozo Katayama , Toshihiro Tanaka , Yutaka Shinagawa , Hiroshi Watase , Takeo Kanai , Nobutaka Nagasaki
发明人： Masatoshi Takahashi , Takanori Yamazoe , Kozo Katayama , Toshihiro Tanaka , Yutaka Shinagawa , Hiroshi Watase , Takeo Kanai , Nobutaka Nagasaki
CPC分类号： G07F7/1008 , G06Q20/341 , G06Q20/40975 , G07F7/084 , G11C11/005 , G11C16/0425 , G11C16/0433 , G11C16/16
摘要： A semiconductor processing device according to the invention includes a first non-volatile memory (21) for erasing stored information on a first data length unit, a second non-volatile memory (22) for erasing stored information on a second data length unit, and a central processing unit (2), and capable of inputting/outputting encrypted data from/to an outside. The first non-volatile memory is used for storing an encryption key to be utilized for encrypting the data. The second non-volatile memory is used for storing a program to be processed by the central processing unit. The non-volatile memories to be utilized for storing the program and for storing the encryption key are separated from each other, and the data lengths of the erase units of information to be stored in the non-volatile memories are defined separately. Therefore, the stored information can efficiently be erased before the execution of a processing of writing the program, and the stored information can be erased corresponding to the data length of a necessary processing unit in the write of the encryption key to be utilized in the calculation processing of the CPU.
摘要翻译： 根据本发明的半导体处理装置包括用于擦除第一数据长度单元上存储的信息的第一非易失性存储器（21），用于擦除第二数据长度单元上存储的信息的第二非易失性存储器（22），以及 中央处理单元（2），能够从/向外部输入/输出加密数据。 第一非易失性存储器用于存储要用于加密数据的加密密钥。 第二非易失性存储器用于存储要由中央处理单元处理的程序。 用于存储程序和用于存储加密密钥的非易失性存储器彼此分离，并且存储在非易失性存储器中的信息的擦除单元的数据长度被分开地定义。 因此，在执行写入程序的处理之前可以有效地擦除存储的信息，并且可以根据在计算中要使用的加密密钥的写入中的必要处理单元的数据长度来擦除存储的信息 处理CPU。
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公开(公告)号：US20110246860A1
公开(公告)日：2011-10-06
申请号：US13162180
申请日：2011-06-16
申请人： Yutaka SHINAGAWA , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
发明人： Yutaka SHINAGAWA , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
CPC分类号： G11C16/349 , G11C16/06 , G11C16/3495
摘要： A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed In an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior In a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more.
摘要翻译： 半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写非易失性存储区域。 非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。 第一非易失性存储区具有用于存储大于第二非易失性存储区的信息的阈值电压的最大变化宽度。 当用于存储信息的阈值电压的最大变化幅度较大时，由于由于存储信息的重写操作而对存储单元的应力变大，所以不利于保证重写操作的次数; 然而，由于读取电流变大，因此可以加快存储器信息的读取速度。 可以优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以对第二非易失性存储器区域进行优先排列以保证存储器信息的重写操作的次数更多。
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公开(公告)号：US07978545B2
公开(公告)日：2011-07-12
申请号：US12775377
申请日：2010-05-06
申请人： Yutaka Shinagawa , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
发明人： Yutaka Shinagawa , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
IPC分类号： G11C7/00
CPC分类号： G11C16/349 , G11C16/06 , G11C16/3495
摘要： A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more.
摘要翻译： 半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写的非易失性存储区域。 非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。 第一非易失性存储区具有用于存储大于第二非易失性存储区的信息的阈值电压的最大变化宽度。 当用于存储信息的阈值电压的最大变化幅度较大时，由于由于存储信息的重写操作而对存储单元的应力变大，所以在保证重写操作次数方面较差; 然而，由于读取电流变大，因此可以加快存储器信息的读取速度。 可以优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以对第二非易失性存储器区域进行优先排列以保证存储器信息的重写操作的次数更多。
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公开(公告)号：US20100220531A1
公开(公告)日：2010-09-02
申请号：US12775377
申请日：2010-05-06
申请人： YUTAKA SHINAGAWA , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
发明人： YUTAKA SHINAGAWA , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
CPC分类号： G11C16/349 , G11C16/06 , G11C16/3495
摘要： A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more.
摘要翻译： 半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写的非易失性存储区域。 非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。 第一非易失性存储区具有用于存储大于第二非易失性存储区的信息的阈值电压的最大变化宽度。 当用于存储信息的阈值电压的最大变化幅度较大时，由于由于存储信息的重写操作而对存储单元的应力变大，所以在保证重写操作次数方面较差; 然而，由于读取电流变大，因此可以加快存储器信息的读取速度。 可以优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以对第二非易失性存储器区域进行优先排列以保证存储器信息的重写操作的次数更多。
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公开(公告)号：US20100160206A1
公开(公告)日：2010-06-24
申请号：US12601214
申请日：2008-07-09
CPC分类号： C11D1/29 , A61K8/86 , A61Q5/02 , A61Q19/10 , B01F17/0057 , C07C303/24 , C07C305/10
摘要： The invention relates to a surfactant composition containing an alkyl ether sulfate represented by the following formula (1): RO—(PO)m(EO)nSO3M (1) wherein R represents a linear alkyl group having 8 to 24 carbon atoms, PO and EO represent a propyleneoxy group and an ethyleneoxy group, respectively, m and n denote the average numbers of added moles of PO and EO, respectively, and are numbers meeting: 0
摘要翻译： 本发明涉及含有下式（1）表示的烷基醚硫酸盐的表面活性剂组合物：RO-（PO）m（EO）nSO3M（1）其中R表示碳原子数为8〜24的直链烷基，PO和 EO分别表示丙烯氧基和亚乙基氧基，m和n分别表示PO和EO的平均加成摩尔数，分别满足：0
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