公开(公告)号：US20130313643A1

公开(公告)日：2013-11-28

申请号：US13478154

申请日：2012-05-23

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Steven J. Holmes ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Shom Ponoth ,  Raghavasimhan Sreenivasan ,  Stefan Schmitz

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Steven J. Holmes ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Shom Ponoth ,  Raghavasimhan Sreenivasan ,  Stefan Schmitz

IPC分类号： H01L27/12 ,  H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823835 ,  H01L21/823842

摘要： A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.

摘要翻译： 一种用于形成电气装置的方法，包括在半导体衬底上形成高k栅介质层，该半导体衬底被图案化以将存在于第一导电器件区域上的高k栅介质层的第一部分与第二部分分离 存在于第二导电装置区域上的高k栅介质层。 连接栅极导体形成在高k栅介质层的第一部分和第二部分上。 连接栅极导体从隔离区域上的第一导电器件区域延伸到第二导电器件区域。 然后可以将第一导电器件区域和第二导电器件区域中的一个暴露于含氧气氛中。 用含氧气氛曝光改变暴露的半导体器件的阈值电压。

公开(公告)号：US08552487B2

公开(公告)日：2013-10-08

申请号：US13568601

申请日：2012-08-07

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC分类号： H01L27/108

CPC分类号： H01L27/1203 ,  H01L27/10829 ,  H01L27/10867

摘要： A semiconductor structure includes a SOI substrate having a top silicon layer overlying an insulation layer, which overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, which device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlying the doped portion, the backside strap being coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlying the first portion.

摘要翻译： 半导体结构包括：SOI衬底，其具有覆盖在底部硅层上的绝缘层的顶部硅层; 至少部分地设置在绝缘层中的电容器; 至少部分地设置在顶部硅层上的器件，该器件耦合到顶部硅层的掺杂部分; 第一外延沉积材料的背面带，位于掺杂部分下面的背侧带的至少第一部分，背面带在背面带的第一端处耦合到顶部硅层的掺杂部分，并且连接到电容器 在背面带的第二端; 以及第二外延沉积材料，其至少部分地覆盖在顶部硅层的掺杂部分上，第二外延沉积材料进一步至少部分地覆盖在第一部分上。

公开(公告)号：US08486776B2

公开(公告)日：2013-07-16

申请号：US12886881

申请日：2010-09-21

申请人： Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Katherine L. Saenger

发明人： Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Katherine L. Saenger

IPC分类号： H01L21/00

CPC分类号： H01L21/84 ,  H01L21/823807

摘要： Strained Si and strained SiGe on insulator devices, methods of manufacture and design structures is provided. The method includes growing an SiGe layer on a silicon on insulator wafer. The method further includes patterning the SiGe layer into PFET and NFET regions such that a strain in the SiGe layer in the PFET and NFET regions is relaxed. The method further includes amorphizing by ion implantation at least a portion of an Si layer directly underneath the SiGe layer. The method further includes performing a thermal anneal to recrystallize the Si layer such that a lattice constant is matched to that of the relaxed SiGe, thereby creating a tensile strain on the NFET region. The method further includes removing the SiGe layer from the NFET region. The method further includes performing a Ge process to convert the Si layer in the PFET region into compressively strained SiGe.

摘要翻译： 应变Si和应变SiGe绝缘体器件，制造方法和设计结构。 该方法包括在绝缘体上硅晶片上生长SiGe层。 该方法还包括将SiGe层图案化成PFET和NFET区域，使得PFET和NFET区域中的SiGe层中的应变被放宽。 该方法还包括通过离子注入直接在SiGe层下面的Si层的至少一部分而非晶化。 该方法还包括进行热退火以使Si层重结晶，使得晶格常数与弛豫SiGe的晶格常数相匹配，从而在NFET区域上产生拉伸应变。 该方法还包括从NFET区域去除SiGe层。 该方法还包括执行Ge工艺以将PFET区域中的Si层转换为压缩应变的SiGe。

公开(公告)号：US08450807B2

公开(公告)日：2013-05-28

申请号：US12719934

申请日：2010-03-09

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC分类号： H01L21/70

CPC分类号： H01L29/66477 ,  H01L21/28518 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/456 ,  H01L29/66628 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for forming a field effect transistor with reduced contact resistance are provided. The reduced contact resistance is manifested by a reduced metal semiconductor alloy contact resistance and a reduced conductively filled via contact-to-metal semiconductor alloy contact resistance. The reduced contact resistance is achieved in this disclosure by texturing the surface of the transistor's source region and/or the transistor's drain region. Typically, both the source region and the drain region are textured in the present disclosure. The textured source region and/or the textured drain region have an increased area as compared to a conventional transistor that includes a flat source region and/or a flat drain region. A metal semiconductor alloy, e.g., a silicide, is formed on the textured surface of the source region and/or the textured surface of the drain region. A conductively filled via contact is formed atop the metal semiconductor alloy.

摘要翻译： 提供了形成具有降低的接触电阻的场效应晶体管的方法和结构。 降低的接触电阻由金属半导体合金接触电阻降低和导电填充通孔接触 - 金属半导体合金接触电阻表现出来。 在本公开内容中通过纹理化晶体管的源极区域和/或晶体管的漏极区域的表面来实现降低的接触电阻。 通常，在本公开内容中，源极区域和漏极区域都被纹理化。 与包括平坦源极区域和/或平坦漏极区域的常规晶体管相比，纹理化源极区域和/或织构化漏极区域具有增加的面积。 在源极区域的纹理表面和/或漏极区域的纹理化表面上形成金属半导体合金，例如硅化物。 在金属半导体合金的顶部形成导电填充的通孔接触。

公开(公告)号：US08445345B2

公开(公告)日：2013-05-21

申请号：US13227750

申请日：2011-09-08

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC分类号： H01L21/8238

CPC分类号： H01L29/51 ,  H01L21/28176 ,  H01L21/823857 ,  H01L21/823864 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66606 ,  H01L29/7833

摘要： A method of forming a complementary metal oxide semiconductor (CMOS) structure having multiple threshold voltage devices includes forming a first transistor device and a second transistor device on a semiconductor substrate. The first transistor device and second transistor device initially have sacrificial dummy gate structures. The sacrificial dummy gate structures are removed and a set of vertical oxide spacers are selectively formed for the first transistor device. The set of vertical oxide spacers are in direct contact with a gate dielectric layer of the first transistor device such that the first transistor device has a shifted threshold voltage with respect to the second transistor device.

摘要翻译： 形成具有多个阈值电压器件的互补金属氧化物半导体（CMOS）结构的方法包括在半导体衬底上形成第一晶体管器件和第二晶体管器件。 第一晶体管器件和第二晶体管器件最初具有牺牲性虚拟栅极结构。 去除牺牲虚拟栅极结构，并且为第一晶体管器件选择性地形成一组垂直氧化物间隔物。 垂直氧化物间隔物组与第一晶体管器件的栅介质层直接接触，使得第一晶体管器件相对于第二晶体管器件具有偏移的阈值电压。

公开(公告)号：US20130105818A1

公开(公告)日：2013-05-02

申请号：US13283308

申请日：2011-10-27

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66636 ,  H01L29/7848 ,  H01L29/78654

摘要： A field effect transistor structure that uses thin semiconductor on insulator channel to control the electrostatic integrity of the device. Embedded stressors are epitaxially grown in the source/drain area from a template in the silicon substrate through an opening made in the buried oxide in the source/drain region. In addition, a dielectric layer is formed between the embedded stressor and the semiconductor region under the buried oxide layer, which is located directly beneath the channel to suppress junction capacitance and leakage.

摘要翻译： 场效应晶体管结构，其使用薄绝缘体上半导体通道来控制器件的静电完整性。 嵌入的应力源在源极/漏极区域中从硅衬底中的模板通过在源极/漏极区域中的掩埋氧化物中形成的开口外延生长。 此外，在嵌入式应力器和位于沟道正下方的掩埋氧化物层下面的半导体区域之间形成介电层，以抑制结电容和漏电。

公开(公告)号：US08362560B2

公开(公告)日：2013-01-29

申请号：US12816697

申请日：2010-06-16

申请人： Pranita Kulkarni ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz

发明人： Pranita Kulkarni ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz

IPC分类号： H01L27/12

CPC分类号： H01L29/66045 ,  H01L21/26506 ,  H01L21/84 ,  H01L27/105 ,  H01L27/1203 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66659

摘要： Embodiments of the present invention provide the ability to fabricate devices having similar physical dimensions, yet with different operating characteristics due to the different effective channel lengths. The effective channel length is controlled by forming an abrupt junction at the boundary of the gate and at least one source or drain. The abrupt junction impacts the diffusion during an anneal process, which in turn controls the effective channel length, allowing physically similar devices on the same chip to have different operating characteristics.

摘要翻译： 本发明的实施例提供了制造具有类似物理尺寸但由于不同有效通道长度而具有不同操作特性的装置的能力。 通过在栅极和至少一个源极或漏极的边界处形成突变结点来控制有效沟道长度。 突变结在退火过程中影响扩散，这又控制有效沟道长度，允许同一芯片上物理上相似的器件具有不同的工作特性。

公开(公告)号：US20130015534A1

公开(公告)日：2013-01-17

申请号：US13184537

申请日：2011-07-16

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/28 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7854

摘要： A three dimensional FET device structure which includes a plurality of three dimensional FET devices. Each of the three dimensional FET devices include an insulating base, a three dimensional fin oriented perpendicular to the insulating base, a gate dielectric wrapped around the three dimensional fin and a gate wrapped around the gate dielectric and extending perpendicularly to the three dimensional fin, the three dimensional fin having a device width being defined as the circumference of the three dimensional fin in contact with the gate dielectric. At least a first of the three dimensional FET devices has a first device width while at least a second of the three dimensional FET devices has a second device width. The first device width is different than the second device width. Also included is a method of making the three dimensional FET device structure.

摘要翻译： 一种三维FET器件结构，其包括多个三维FET器件。 三维FET器件中的每一个包括绝缘基底，垂直于绝缘基底取向的三维鳍片，围绕三维翅片缠绕的栅极电介质和围绕栅极电介质缠绕并垂直于三维翅片延伸的栅极， 具有将器件宽度定义为与栅极电介质接触的三维鳍片的圆周的三维鳍片。 三维FET器件中的至少一个具有第一器件宽度，而三维FET器件中的至少一个具有第二器件宽度。 第一个设备宽度与第二个设备宽度不同。 还包括制造三维FET器件结构的方法。

公开(公告)号：US20120329232A1

公开(公告)日：2012-12-27

申请号：US13602644

申请日：2012-09-04

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC分类号： H01L21/336

CPC分类号： H01L27/1203 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/84 ,  H01L29/66628

摘要： In one exemplary embodiment of the invention, a semiconductor structure includes: a substrate; and a plurality of devices at least partially overlying the substrate, where the plurality of devices include a first device coupled to a second device via a first raised source/drain having a first length, where the first device is further coupled to a second raised source/drain having a second length, where the first device comprises a transistor, where the first raised source/drain and the second raised source/drain at least partially overly the substrate, where the second raised source/drain comprises a terminal electrical contact, where the second length is greater than the first length.

摘要翻译： 在本发明的一个示例性实施例中，半导体结构包括：衬底; 以及至少部分地覆盖所述衬底的多个器件，其中所述多个器件包括经由具有第一长度的第一升高源极/漏极耦合到第二器件的第一器件，其中所述第一器件进一步耦合到第二升高源 /漏极，其中第一器件包括晶体管，其中第一升高源极/漏极和第二升高源极/漏极至少部分地超过衬底，其中第二升高源极/漏极包括端子电接触，其中 第二长度大于第一长度。

公开(公告)号：US20120299075A1

公开(公告)日：2012-11-29

申请号：US13568601

申请日：2012-08-07

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC分类号： H01L27/108

CPC分类号： H01L27/1203 ,  H01L27/10829 ,  H01L27/10867

摘要： In one exemplary embodiment, a semiconductor structure including: a SOI substrate having a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlies the doped portion, the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlies the first portion.

摘要翻译： 在一个示例性实施例中，一种半导体结构，包括：具有覆盖绝缘层的顶部硅层的SOI衬底，所述绝缘层覆盖在底部硅层上; 至少部分地设置在绝缘层中的电容器; 至少部分地设置在顶部硅层上的器件，该器件耦合到顶部硅层的掺杂部分; 第一外延沉积材料的背面带，背面带的至少第一部分位于掺杂部分的下面，背侧带在背面带的第一端和电容器处耦合到顶部硅层的掺杂部分 在背面带的第二端; 以及至少部分地覆盖在顶部硅层的掺杂部分上的第二外延沉积材料，第二外延沉积材料还至少部分地覆盖在第一部分上。