公开(公告)号：US07875875B2

公开(公告)日：2011-01-25

申请号：US11450280

申请日：2006-06-12

申请人： Kenichi Kawaguchi

发明人： Kenichi Kawaguchi

IPC分类号： H01L31/00

CPC分类号： H01L31/035236 ,  B82Y20/00 ,  H01S5/22 ,  H01S5/2275 ,  H01S5/3201 ,  H01S5/3412 ,  H01S5/5009

摘要： A quantum dot semiconductor device securing sufficient gains without depending on polarization and a manufacturing method thereof. On a first barrier layer, a multilayer quantum dot is formed by repeatedly stacking alternately a quantum dot layer and a second barrier layer. On a quantum dot layer as an uppermost layer of the quantum dot, a third barrier layer which keeps local strains in the quantum dot layer is formed. On the third barrier layer, a fourth barrier layer which compensates compressive strains from the second barrier layer is formed. Therefore, the fourth barrier layer made of tensile strain materials compensates accumulation of compressive strains caused by stacking of a multilayer quantum dot layer. The third barrier layer prevents tensile strains in the fourth barrier layer from directly impacting on the quantum dot layer, so that local strains can be effectively cancelled. Thus, the above-described semiconductor device can be realized.

摘要翻译： 量子点半导体器件及其制造方法确保足够的增益而不依赖于极化。 在第一阻挡层上，通过重复堆叠量子点层和第二阻挡层来形成多层量子点。 在作为量子点的最上层的量子点层上形成保持量子点层局部应变的第三势垒层。 在第三阻挡层上形成补偿来自第二阻挡层的压缩应变的第四阻挡层。 因此，由拉伸应变材料制成的第四阻挡层补偿由堆叠多层量子点层引起的压缩应变的累积。 第三阻挡层防止第四阻挡层中的拉伸应变直接影响量子点层，从而可以有效地消除局部应变。 因此，可以实现上述半​​导体器件。

公开(公告)号：US20100306441A1

公开(公告)日：2010-12-02

申请号：US12852137

申请日：2010-08-06

申请人： Kenichi Kawaguchi

发明人： Kenichi Kawaguchi

IPC分类号： G06F13/14

CPC分类号： G06F13/362

摘要： A data transfer apparatus for transferring data between a system bus and a local bus at a high speed is provided. A bus bridge 101 is connected between a system bus 132 and a local bus 137. Data transferred between a CPU 133, an I/O device 136 and a main memory 135 on the system bus 132 are retained in an associative memory 106 via an associative memory control unit 105. When an access to this data from an I/O device 138 on the local bus 137 is generated, the data are transferred from the associative memory 106 to the I/O device 138. Thus, when a data transfer request from the I/O device 138 to the main memory 135 is generated, no bus cycle is generated on the system bus 132 as long as this data are retained in the associative memory 106. Consequently, the data can be transferred at a high speed.

摘要翻译： 提供了一种用于在系统总线和本地总线之间高速传输数据的数据传送装置。 总线桥101连接在系统总线132和本地总线137之间。在CPU 133，I / O设备136和系统总线132上的主存储器135之间传送的数据经由关联式存储器106保留在关联存储器106中 存储器控制单元105.当生成来自本地总线137上的I / O设备138的该数据的访问时，数据从关联存储器106传送到I / O设备138.因此，当数据传输请求 产生从I / O设备138到主存储器135，只要该数据被保留在关联存储器106中，就不会在系统总线132上产生总线周期。因此，可以高速传送数据。

公开(公告)号：US07814257B2

公开(公告)日：2010-10-12

申请号：US11519114

申请日：2006-09-11

申请人： Kenichi Kawaguchi

发明人： Kenichi Kawaguchi

IPC分类号： G06F13/14 ,  G06F13/00

CPC分类号： G06F13/362

摘要： A data transfer apparatus for transferring data between a system bus and a local bus at a high speed is provided. A bus bridge 101 is connected between a system bus 132 and a local bus 137. Data transferred between a CPU 133, an I/O device 136 and a main memory 135 on the system bus 132 are retained in an associative memory 106 via an associative memory control unit 105. When an access to this data from an I/O device 138 on the local bus 137 is generated, the data are transferred from the associative memory 106 to the I/O device 138. Thus, when a data transfer request from the I/O device 138 to the main memory 135 is generated, no bus cycle is generated on the system bus 132 as long as this data are retained in the associative memory 106. Consequently, the data can be transferred at a high speed.

摘要翻译： 提供了一种用于在系统总线和本地总线之间高速传输数据的数据传送装置。 总线桥101连接在系统总线132和本地总线137之间。在CPU 133，I / O设备136和系统总线132上的主存储器135之间传送的数据经由关联式存储器106保留在关联存储器106中 存储器控制单元105.当生成来自本地总线137上的I / O设备138的该数据的访问时，数据从关联存储器106传送到I / O设备138.因此，当数据传输请求 产生从I / O设备138到主存储器135，只要该数据被保留在关联存储器106中，就不会在系统总线132上产生总线周期。因此，可以高速传送数据。

公开(公告)号：US07616675B2

公开(公告)日：2009-11-10

申请号：US11902622

申请日：2007-09-24

申请人： Kenichi Kawaguchi ,  Tsuyoshi Yamamoto

发明人： Kenichi Kawaguchi ,  Tsuyoshi Yamamoto

IPC分类号： H01S5/00

CPC分类号： H01S5/18341 ,  B82Y20/00 ,  H01S5/0207 ,  H01S5/021 ,  H01S5/0261 ,  H01S5/0425 ,  H01S5/18305 ,  H01S5/18308 ,  H01S5/18369 ,  H01S5/3027 ,  H01S5/3036 ,  H01S5/3412 ,  H01S2304/04

摘要： Disclosed is a semiconductor laser device capable of realizing efficient current injection and a method of manufacturing the same. The method includes the steps of: forming a DBR mirror over a Si substrate; forming an n-type conductive layer over the DBR mirror; forming a luminescent layer over a part of the n-type conductive layer; forming an insulating layer over a side surface of the luminescent layer over the n-type conductive layer; forming a p-type conductive layer over the insulating layer and the luminescent layer; forming another DBR mirror over the p-type conductive layer so as to be located immediately above the luminescent layer; forming an electrode electrically connected to the n-type conductive layer; and forming another electrode over the p-type conductive layer.

摘要翻译： 公开了能够实现高效电流注入的半导体激光装置及其制造方法。 该方法包括以下步骤：在Si衬底上形成DBR镜; 在DBR镜上形成n型导电层; 在n型导电层的一部分上形成发光层; 在所述n型导电层的上方在所述发光层的侧面上形成绝缘层; 在绝缘层和发光层上形成p型导体层; 在p型导电层上形成另一个DBR镜，以便位于发光层的正上方; 形成与n型导电层电连接的电极; 并在p型导电层上形成另一电极。

公开(公告)号：US07516262B2

公开(公告)日：2009-04-07

申请号：US12028708

申请日：2008-02-08

申请人： Kenichi Kawaguchi

发明人： Kenichi Kawaguchi

IPC分类号： G06F13/36

CPC分类号： G06F13/4027 ,  G06F13/4031 ,  G06F13/4059 ,  G06F13/423 ,  G06F2213/0024

摘要： A bus bridge is connected to a primary bus and a secondary bus, and relays data between a master and a target which are each connected to a different one of the primary and secondary buses. The bus bridge includes a primary bus interface, a secondary bus interface, a data FIFO, and a register block. The register block, which can be written by the master, includes two registers corresponding to the primary and secondary buses. Relay information showing the number of entries of data to be relayed from the target to the master is registered in a register corresponding to a bus to which the target is connected. In a read transaction, the primary bus interface or the secondary bus interface reads data from the target until data of the amount shown by the registered relay information is stored in the data FIFO.

摘要翻译： 总线桥连接到主总线和辅助总线，并且中继主机和目标之间的数据，每个主站和目标站之间连接到主总线和次总线之间的不同的总线。 总线桥包括主总线接口，辅助总线接口，数据FIFO和寄存器块。 可由主器件写入的寄存器块包括与主母线和辅助母线相对应的两个寄存器。 显示要从目标到主机中继的数据的条目数的中继信息被登记在对应于目标连接到的总线的寄存器中。 在读取事务中，主总线接口或辅助总线接口从目标读取数据，直到被注册的中继信息所示量的数据被存储在数据FIFO中。

公开(公告)号：US20080183936A1

公开(公告)日：2008-07-31

申请号：US11936425

申请日：2007-11-07

申请人： Kenichi Kawaguchi

发明人： Kenichi Kawaguchi

IPC分类号： G06F13/36

CPC分类号： G06F13/4031

摘要： A bus bridge is connected to a first bus and a second bus. In the bus bridge, an arbiter grants ownership of the first bus to one of a plurality of devices connected to the first bus. A detecting unit detects a read cycle initiated by the device on the first bus to read data from a memory which is also accessible by another device connected to the second bus. A first signaling unit sends a first signal to the arbiter, when the data is not yet transferable to the device when the read cycle is detected. A second signaling unit sends a second signal to the arbiter, when the data becomes transferable to the device. The arbiter deprives the device of the ownership of the first bus upon receipt of the first signal, and withholds from granting the ownership to the device until receipt of the second signal.

摘要翻译： 总线桥连接到第一总线和第二总线。 在总线桥中，仲裁者将第一总线的所有权授予连接到第一总线的多个设备之一。 检测单元检测由第一总线上的设备发起的读周期，以从存储器读取数据，该存储器也可由连接到第二总线的另一设备访问。 当检测到读取周期时，当数据不能传输到设备时，第一信令单元向仲裁器发送第一信号。 当数据可转移到设备时，第二信令单元向仲裁器发送第二信号。 仲裁者在收到第一个信号后，剥夺了第一个公共汽车的所有权，并将所有权授予设备，直到收到第二个信号。

公开(公告)号：US07360009B2

公开(公告)日：2008-04-15

申请号：US11623685

申请日：2007-01-16

申请人： Kenichi Kawaguchi

发明人： Kenichi Kawaguchi

IPC分类号： G06F13/36

CPC分类号： G06F13/4027 ,  G06F13/4031 ,  G06F13/4059 ,  G06F13/423 ,  G06F2213/0024

摘要： A bus bridge is connected to a primary bus and a secondary bus, and relays data between a master and a target which are each connected to a different one of the primary and secondary buses. The bus bridge includes a primary bus interface, a secondary bus interface, a data FIFO, and a register block. The register block, which can be written by the master, includes two registers corresponding to the primary and secondary buses. Relay information showing the number of entries of data to be relayed from the target to the master is registered in a register corresponding to a bus to which the target is connected. In a read transaction, the primary bus interface or the secondary bus interface reads data from the target until data of the amount shown by the registered relay information is stored in the data FIFO.

摘要翻译： 总线桥连接到主总线和辅助总线，并且中继主机和目标之间的数据，每个主站和目标站之间连接到主总线和次总线之间的不同的总线。 总线桥包括主总线接口，辅助总线接口，数据FIFO和寄存器块。 可由主器件写入的寄存器块包括与主母线和辅助母线相对应的两个寄存器。 显示要从目标到主机中继的数据的条目数的中继信息被登记在对应于目标连接到的总线的寄存器中。 在读取事务中，主总线接口或辅助总线接口从目标读取数据，直到被注册的中继信息所示量的数据被存储在数据FIFO中。

公开(公告)号：US20080080573A1

公开(公告)日：2008-04-03

申请号：US11902622

申请日：2007-09-24

申请人： Kenichi Kawaguchi ,  Tsuyoshi Yamamoto

发明人： Kenichi Kawaguchi ,  Tsuyoshi Yamamoto

IPC分类号： H01S5/06 ,  H01L33/00 ,  H01S5/026

CPC分类号： H01S5/18341 ,  B82Y20/00 ,  H01S5/0207 ,  H01S5/021 ,  H01S5/0261 ,  H01S5/0425 ,  H01S5/18305 ,  H01S5/18308 ,  H01S5/18369 ,  H01S5/3027 ,  H01S5/3036 ,  H01S5/3412 ,  H01S2304/04

摘要： Disclosed is a semiconductor laser device capable of realizing efficient current injection and a method of manufacturing the same. The method includes the steps of: forming a DBR mirror over a Si substrate; forming an n-type conductive layer over the DBR mirror; forming a luminescent layer over a part of the n-type conductive layer; forming an insulating layer over a side surface of the luminescent layer over the n-type conductive layer; forming a p-type conductive layer over the insulating layer and the luminescent layer; forming another DBR mirror over the p-type conductive layer so as to be located immediately above the luminescent layer; forming an electrode electrically connected to the n-type conductive layer; and forming another electrode over the p-type conductive layer.

摘要翻译： 公开了能够实现高效电流注入的半导体激光装置及其制造方法。 该方法包括以下步骤：在Si衬底上形成DBR镜; 在DBR镜上形成n型导电层; 在n型导电层的一部分上形成发光层; 在所述n型导电层的上方在所述发光层的侧面上形成绝缘层; 在绝缘层和发光层上形成p型导体层; 在p型导电层上形成另一个DBR镜，以便位于发光层的正上方; 形成与n型导电层电连接的电极; 并在p型导电层上形成另一电极。

公开(公告)号：US20070210300A1

公开(公告)日：2007-09-13

申请号：US11450280

申请日：2006-06-12

申请人： Kenichi Kawaguchi

发明人： Kenichi Kawaguchi

IPC分类号： H01L31/00

CPC分类号： H01L31/035236 ,  B82Y20/00 ,  H01S5/22 ,  H01S5/2275 ,  H01S5/3201 ,  H01S5/3412 ,  H01S5/5009

摘要： A quantum dot semiconductor device securing sufficient gains without depending on polarization and a manufacturing method thereof. On a first barrier layer, a multilayer quantum dot is formed by repeatedly stacking alternately a quantum dot layer and a second barrier layer. On a quantum dot layer as an uppermost layer of the quantum dot, a third barrier layer which keeps local strains in the quantum dot layer is formed. On the third barrier layer, a fourth barrier layer which compensates compressive strains from the second barrier layer is formed. Therefore, the fourth barrier layer made of tensile strain materials compensates accumulation of compressive strains caused by stacking of a multilayer quantum dot layer. The third barrier layer prevents tensile strains in the fourth barrier layer from directly impacting on the quantum dot layer, so that local strains can be effectively cancelled. Thus, the above-described semiconductor device can be realized.

摘要翻译： 量子点半导体器件及其制造方法确保足够的增益而不依赖于极化。 在第一阻挡层上，通过重复堆叠量子点层和第二阻挡层来形成多层量子点。 在作为量子点的最上层的量子点层上形成保持量子点层局部应变的第三势垒层。 在第三阻挡层上形成补偿来自第二阻挡层的压缩应变的第四阻挡层。 因此，由拉伸应变材料制成的第四阻挡层补偿由堆叠多层量子点层引起的压缩应变的累积。 第三阻挡层防止第四阻挡层中的拉伸应变直接影响量子点层，从而可以有效地消除局部应变。 因此，可以实现上述半​​导体器件。

公开(公告)号：US07228436B2

公开(公告)日：2007-06-05

申请号：US10611879

申请日：2003-07-03

申请人： Kenichi Kawaguchi

发明人： Kenichi Kawaguchi

IPC分类号： G06F11/30

CPC分类号： G06F21/14 ,  G06F12/1408 ,  G06F12/1433 ,  G06F21/10

摘要： When an encrypted program and a decryption program are inputted to a first memory, a semiconductor integrated circuit device causes a bus port to disable access from the outside and enables access to the first memory and to a second memory, thereby transferring the encrypted program and the decryption program from the first memory to the second memory. When the transfer is completed, the semiconductor integrated circuit device disables access to the first memory and gives, to a CPU, an instruction to decrypt the encrypted program by using a secret key held in a secret key holder and the decryption program and execute the decrypted program. After the execution of the decrypted program is completed, the semiconductor integrated circuit device disables access to the second memory.