公开(公告)号：US12158795B2

公开(公告)日：2024-12-03

申请号：US18074751

申请日：2022-12-05

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Shay Aisman ,  Ariel Almog ,  Ran Avraham Koren

IPC: G06F1/04 ,  G06F11/07

Abstract: A device includes a hardware block to perform a hardware process and internal logic coupled between a processing device, which executes instructions, and the hardware block. The internal logic can one of measure execution time or count clock cycles of at least a portion of the hardware process. The internal logic can further, in response to the measured execution time or the counted clock cycles satisfying a predetermined condition, provide data associated with the one of the execution time measurement or the clock cycles count to the processing device, the data being statistically indicative of a latency of data packets sent by the hardware process over a total time the hardware process executes.

公开(公告)号：US20240373379A1

公开(公告)日：2024-11-07

申请号：US18225525

申请日：2023-07-24

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Liron Mula ,  Ariel Almog ,  Bar Shapira ,  Guy Lederman

IPC: H04W56/00

Abstract: A system including an interconnect device coupled with one or more devices where the first device of the one or more devices is to transmit a control block for synchronization via a physical layer of a link coupled to the high-speed interconnect device, the control block comprising a header portion of bits corresponding to a header indicating the block is a control block and a data portion of bits indicating the control block is associated with time synchronization information. The interconnect device is to receive data, parse the data, determine the data is associated with the control block, determine a delay associated with the physical layer transmitting the control block and transmitting a signal responsive to receiving the control block and determining the delay.

公开(公告)号：US20240373378A1

公开(公告)日：2024-11-07

申请号：US18143509

申请日：2023-05-04

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Ran Ravid ,  Guy Lederman ,  Liron Mula ,  Eitan Zahavi ,  Peter Paneah

IPC: H04W56/00

Abstract: A system including a device coupled with a link and including a transmitter. The device is to generate a control block for synchronization via a physical layer of the link, the control block including a header portion of bits corresponding to a header indicating the message is a control block and a data portion of bits including synchronization information for synchronizing via the physical layer. The device is further to transmit, via the link, the control block comprising the header portion of bits and the data portion of bits.

公开(公告)号：US20240372691A1

公开(公告)日：2024-11-07

申请号：US18367383

申请日：2023-09-12

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Maciek Machnikowski

IPC: H04L7/00

Abstract: A system includes a device including a transmitter associated with a link coupled to the device. The device is to receive from an application layer of the device, a first bitstream for transmission. The device is to encode the first bitstream into one or more blocks and transmit the one or more data blocks via the link. The device is also to receive a second bitstream to be transmitted. The device is to encode the second bitstream into a control block and transmit the control block via the link. The control block includes a first portion of bits corresponding to a header indicating the control block includes the second bitstream and a second portion of bits including the second bitstream.

公开(公告)号：US20240333915A1

公开(公告)日：2024-10-03

申请号：US18738013

申请日：2024-06-09

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan David Levi ,  Assaf Weissman ,  Kobi Pines ,  Noam Bloch ,  Erez Yaacov ,  Ariel Naftali Cohen

IPC: H04N19/105 ,  H04N19/139 ,  H04N19/147 ,  H04N19/176

CPC classification number: H04N19/105 ,  H04N19/139 ,  H04N19/176 ,  H04N19/147

Abstract: A system for video encoding includes an acceleration device, to select from a video stream a target video frame and one or more reference frames. The target and reference frames are divided into respective first pluralities of first blocks of a first size and into respective second pluralities of second blocks of a second size, larger than the first size. At least a first map and a second map are computed, including respective motion vectors between each first block in the target video frame and corresponding first blocks in the reference frames, and between each second block in the target video frame and corresponding second blocks in the one or more reference frames. A control unit encodes the target video frame based on at least one of the reference frames by selecting motion vectors from among the motion vectors in the first and second maps.

公开(公告)号：US20240311184A1

公开(公告)日：2024-09-19

申请号：US18495749

申请日：2023-10-26

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Wojciech Wasko ,  Dotan David Levi ,  Ariel Shahar ,  Roee Moyal ,  Eliel Peretz

IPC: G06F9/48 ,  G06F11/34

CPC classification number: G06F9/4881 ,  G06F11/3409

Abstract: A work descriptor identifying a plurality of workflow tasks to be performed by a hardware device is generated by a host system. The work descriptor corresponds to a performance completion message generated by the hardware device in response to completing performance of the work descriptor. One or more completion indicators are added to the work descriptor. Each of the completion indicators instructs the hardware device to generate one or more additional completion messages during performance of the work descriptor in response to a trigger criterion. The work descriptor is caused to be available to the hardware device for execution.

公开(公告)号：US11907754B2

公开(公告)日：2024-02-20

申请号：US17549949

申请日：2021-12-14

Applicant: Mellanox Technologies, Ltd.

Inventor： Wojciech Wasko ,  Dotan David Levi ,  Liron Mula ,  Natan Manevich

IPC: G06F9/48 ,  G06F1/08 ,  G06F13/16

CPC classification number: G06F9/4825 ,  G06F1/08 ,  G06F9/485 ,  G06F13/1689

Abstract: In one embodiment, a system includes a memory, a processing device including a device processor; and a device clock, and a peripheral device including an interface to share data with the processing device, a hardware clock, and processing circuitry to write respective interrupt signaling messages to the memory responsively to respective hardware clock values of the hardware clock, and wherein the device processor is configured, responsively to the respective interrupt signaling messages being written to the memory, to perform a time-dependent action.

公开(公告)号：US20240031124A1

公开(公告)日：2024-01-25

申请号：US17868841

申请日：2022-07-20

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Wojciech Wasko ,  Natan Manevich

IPC: H04L7/027 ,  H04L12/40

CPC classification number: H04L7/027 ,  H04L12/40

Abstract: In one embodiment, a clock syntonization system includes a first compute node including a first physical hardware clock to operate at a first clock frequency, a second compute node, and an interconnect data bus to transfer data from the first compute node at a data rate indicative of the first clock frequency of the first physical hardware clock, and wherein the second compute node includes clock synchronization circuitry to derive a second clock frequency from the data rate of the transferred data, and provide a clock signal at the derived second clock frequency.

公开(公告)号：US11853116B2

公开(公告)日：2023-12-26

申请号：US17582058

申请日：2022-01-24

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Wojciech Wasko ,  Eitan Zahavi ,  Natan Manevich ,  Bar Shapira

IPC: G06F1/14 ,  H04J3/06 ,  G06F1/12

CPC classification number: G06F1/14 ,  G06F1/12 ,  H04J3/0661 ,  H04J3/0679 ,  H04J3/0682 ,  H04J3/0697

Abstract: In one embodiment, a device includes a hardware clock to maintain a clock value, a hardware counter to maintain an estimation of a dynamic error bound of the clock value, and a clock controller to intermittently discipline the hardware clock responsively to a remote clock, advance the hardware counter at a rate responsively to a clock drift, and adjust the hardware counter responsively to the hardware clock being disciplined.

公开(公告)号：US20230367358A1

公开(公告)日：2023-11-16

申请号：US17867779

申请日：2022-07-19

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Ariel Almog ,  Bar Shapira

IPC: G06F1/12 ,  G06F1/10 ,  G06F1/06

CPC classification number: G06F1/12 ,  G06F1/10 ,  G06F1/06

Abstract: In one embodiment, a synchronized communication system includes a first network device and a second network device, wherein the first network device includes a first physical hardware clock, and is configured to recover a reference clock time from packets received from a remote clock, find a clock differential between a clock time output by the first physical hardware clock and the recovered reference clock time, provide a control signal to the second network device responsively to the clock differential, and the second network device includes a second physical hardware clock, and is configured to adjust a clock time output by the second physical hardware clock responsively to the control signal.