公开(公告)号：US20220327060A1

公开(公告)日：2022-10-13

申请号：US17809136

申请日：2022-06-27

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F12/0882 ,  G06F12/0868 ,  G06F9/54 ,  G06F11/10 ,  G06F11/30 ,  G06F9/50 ,  G11C5/06

Abstract: Techniques and devices are described for embedding data in an address stream on an interconnect, such as a memory bus. Addresses in an address stream indicate at least part of a location in memory (e.g., a memory page and offset), whereas data embedded in the address stream can indicate when metadata or other information is available to lend context to the addresses in the address stream. The indication of data in the address stream can be communicated using, for example, a mailbox, a preamble message in a messaging protocol, a checksum, repetitive transmission, or combinations thereof. The indication of data can be recorded from the address stream and may later be used to interpret memory traces recorded during a test or can be used to communicate with a memory device or other recipient of the data during testing or regular operations.

公开(公告)号：US11442854B2

公开(公告)日：2022-09-13

申请号：US17070774

申请日：2020-10-14

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F12/02 ,  G06F12/0802

Abstract: Described apparatuses and methods balance memory-portion accessing. Some memory architectures are designed to accelerate memory accesses using schemes that may be at least partially dependent on memory access requests being distributed roughly equally across multiple memory portions of a memory. Examples of such memory portions include cache sets of cache memories and memory banks of multibank memories. Some code, however, may execute in a manner that concentrates memory accesses in a subset of the total memory portions, which can reduce memory responsiveness in these memory types. To account for such behaviors, described techniques can shuffle memory addresses based on a shuffle map to produce shuffled memory addresses. The shuffle map can be determined based on a count of the occurrences of a reference bit value at bit positions of the memory addresses. Using the shuffled memory address for memory requests can substantially balance the accesses across the memory portions.

公开(公告)号：US20220223201A1

公开(公告)日：2022-07-14

申请号：US17146314

申请日：2021-01-11

Applicant: Micron Technology, Inc.

Inventor： Aliasger Tayeb Zaidy ,  Patrick Alan Estep ,  David Andrew Roberts

IPC: G11C11/54 ,  G06N3/063 ,  G06N3/08 ,  G06F12/0862 ,  G06F12/0897

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, the accelerator can have processing units to perform at least matrix computations of an artificial neural network via execution of instructions. The processing units have a local memory store operands of the instructions. The accelerator can access a random access memory via a system buffer, or without going through the system buffer. A fetch instruction can request an item, available at a memory address in the random access memory, to be loaded into the local memory at a local address. The fetch instruction can include a hint for the caching of the item in the system buffer. During execution of the instruction, the hint can be used to determine whether to load the item through the system buffer or to bypass the system buffer in loading the item.

公开(公告)号：US20220113881A1

公开(公告)日：2022-04-14

申请号：US17070815

申请日：2020-10-14

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F3/06

Abstract: Described apparatuses and methods control a voltage or a temperature of a memory domain to balance memory performance and energy use. In some aspects, an adaptive controller monitors memory performance metrics of a host processor that correspond to commands made to a memory domain of a memory system, including one operating at cryogenic temperatures. Based on the memory performance metrics, the adaptive controller can determine memory performance demand of the host processor, such as latency demand or bandwidth demand, for the memory domain. The adaptive controller may alter, using the determined performance demand, a voltage or a temperature of the memory domain to enable memory access performance that is tailored to meet the demand of the host processor. By so doing, the adaptive controller can manage various settings of the memory domain to address short- or long-term changes in memory performance demand.

公开(公告)号：US20220019530A1

公开(公告)日：2022-01-20

申请号：US16937671

申请日：2020-07-24

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F12/06

Abstract: Described apparatuses and methods track access metadata pertaining to activity within respective address ranges. The access metadata can be used to inform prefetch operations within the respective address ranges. The prefetch operations may involve deriving access patterns from access metadata covering the respective ranges. Suitable address range sizes for accurate pattern detection, however, can vary significantly from region to region of the address space based on, inter alia, workloads produced by programs utilizing the regions. Advantageously, the described apparatuses and methods can adapt the address ranges covered by the access metadata for improved prefetch performance. A data structure may be used to manage the address ranges in which access metadata are tracked. The address ranges can be adapted to improve prefetch performance through low-overhead operations implemented within the data structure. The data structure can encode hierarchical relationships that ensure the resulting address ranges are distinct.

公开(公告)号：US11194728B2

公开(公告)日：2021-12-07

申请号：US16525106

申请日：2019-07-29

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F12/0888 ,  G06F12/0897 ,  G06F12/0862

Abstract: Systems, apparatuses, and methods related to memory management are described. For example, these may include a first memory level including memory pages in a memory array, a second memory level including a cache, a pre-fetch buffer, or both, and a memory controller that determines state information associated with a memory page in the memory array targeted by a memory access request. The state information may include a first parameter indicative of a current activation state of the memory page and a second parameter indicative of statistical likelihood (e.g., confidence) that a subsequent memory access request will target the memory page. The memory controller may disable storage of data associated with the memory page in the second memory level when the first parameter associated with the memory page indicates that the memory page is activated and the second parameter associated with the memory page is greater than or equal to a threshold.

公开(公告)号：US20210365380A1

公开(公告)日：2021-11-25

申请号：US16879688

申请日：2020-05-20

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F12/0882 ,  G06F12/0868 ,  G06F9/54 ,  G06F9/50 ,  G06F11/30 ,  G06F11/10

Abstract: Techniques and devices are described for embedding data in an address stream on an interconnect, such as a memory bus. Addresses in an address stream indicate at least part of a location in memory (e.g., a memory page and offset), whereas data embedded in the address stream can indicate when metadata or other information is available to lend context to the addresses in the address stream. The indication of data in the address stream can be communicated using, for example, a mailbox, a preamble message in a messaging protocol, a checksum, repetitive transmission, or combinations thereof. The indication of data can be recorded from the address stream and may later be used to interpret memory traces recorded during a test or can be used to communicate with a memory device or other recipient of the data during testing or regular operations.

公开(公告)号：US20210318958A1

公开(公告)日：2021-10-14

申请号：US16846266

申请日：2020-04-10

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski ,  Elliott Clifford Cooper-Balis ,  David Andrew Roberts

IPC: G06F12/084 ,  G06F12/0853 ,  G06F12/02 ,  G06F9/30 ,  G06F13/16

Abstract: Described apparatuses and methods order memory address portions advantageously for cache-memory addressing. An address bus can have a smaller width than a memory address. The multiple bits of the memory address can be separated into most-significant bits (MSB) and least-significant bits (LSB) portions. The LSB portion is provided to a cache first. The cache can process the LSB portion before the MSB portion is received. The cache can use index bits of the LSB portion to index into an array of memory cells and identify multiple corresponding tags. The cache can also check the corresponding tags against lower tag bits of the LSB portion. A partial match may be labeled as a predicted hit, and a partial miss may be labeled as an actual miss, which can initiate a data fetch. With the remaining tag bits from the MSB portion, the cache can confirm or refute the predicted hit.

公开(公告)号：US20210318922A1

公开(公告)日：2021-10-14

申请号：US16846259

申请日：2020-04-10

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F11/07 ,  G06F11/10 ,  G06N3/08

Abstract: Methods, systems, and apparatuses related to a memory fault map for an accelerated neural network. An artificial neural network can be accelerated by operating memory outside of the memory's baseline operating parameters. Doing so, however, often increases the amount of faulty data locations in the memory. Through creation and use of the disclosed fault map, however, artificial neural networks can be trained more quickly and using less bandwidth, which reduces the neural networks' sensitivity to these additional faulty data locations. Hardening a neural network to these memory faults allows the neural network to operate effectively even when using memory outside of that memory's baseline operating parameters.

公开(公告)号：US20210271614A1

公开(公告)日：2021-09-02

申请号：US16804895

申请日：2020-02-28

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts ,  Joseph Thomas Pawlowski ,  Elliott Cooper-Balis

IPC: G06F13/16 ,  G06F3/06 ,  G06F1/10 ,  G06F1/324

Abstract: Techniques for implementing and/or operating an apparatus, which includes a host system, a memory system, and a shared memory bus. The memory system includes a first memory type that is subject to a first memory type-specific timing constraint and a second memory type that is subject to a second memory type-specific timing constraint. Additionally, the shared memory bus is shared by the first memory type and the second memory type. Furthermore, the apparatus utilizes a first time period to communicate with the first memory type via the shared memory bus at least in part by enforcing the first memory type-specific timing constraint during the first time period and utilizes a second time period to communicate with the second memory type via the shared memory bus at least in part by enforcing the second memory type-specific timing constraint during the second time period.