公开(公告)号：US12001715B2

公开(公告)日：2024-06-04

申请号：US17557818

申请日：2021-12-21

Applicant: Micron Technology, Inc.

Inventor： Dean D. Gans

IPC: G06F3/06 ,  G06F12/1009

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F12/1009 ,  G06F2212/65

Abstract: Methods, systems, and devices for memory with a virtual page size are described. Memory cells may be accessed in portions or page sizes that are tailored to a particular use or application. A variable page size may be defined that represents a subset or superset of memory cells in a nominal page size for the array. For example, memory cells associated with a page size of a memory array may be accessed with commands to a memory array. Each command may contain a particular addressing scheme based on the page size of the memory array and may activate one or more sets of memory cells within the array. The addressing scheme may be modified based on the page size of the memory array. Upon activating a desired set of memory cells, one or more individual activated cells may be accessed.

公开(公告)号：US11955977B2

公开(公告)日：2024-04-09

申请号：US17501858

申请日：2021-10-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dean D. Gans

IPC: G11C7/22 ,  G11C7/00 ,  G11C8/18 ,  G11C11/4076 ,  G11C29/00 ,  G11C29/02 ,  G11C29/50 ,  H03K5/156 ,  G11C7/10

CPC classification number: H03K5/1565 ,  G11C7/00 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4076 ,  G11C29/00 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C7/1045 ,  G11C2207/2254

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for lookahead duty cycle adjustment of a clock signal. Clock signals may be provided to a semiconductor device, such as a memory device, to synchronize one or more operations. A duty cycle adjuster (DCA) of the device may adjust the clock signal(s) based on a duty code determined during an initialization of the device. While the device is in operation, a lookahead DCA (LA DCA) may test a number of different adjustments to the clock signal(s), the results of which may be determined by a duty cycle monitor (DCM). The results of the DCM may be used to select one of the tested adjustments, which may be used to update the duty code.

公开(公告)号：US11955162B2

公开(公告)日：2024-04-09

申请号：US18312747

申请日：2023-05-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dean D. Gans ,  John D. Porter

IPC: G06F3/06 ,  G06F13/16 ,  G11C11/4074 ,  G11C11/4076

CPC classification number: G11C11/4076 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/1689 ,  G11C11/4074

Abstract: Apparatuses and methods for input receiver circuits and receiver masks for electronic memory are disclosed. Embodiments of the disclosure include memory receiver masks having shapes other than rectangular shapes. For example, a receiver mask according to some embodiments of the disclosure may have a hexagonal shape. Other shapes of receiver masks may also be included in other embodiments of the disclosure. Circuits, timing, and operating parameters for achieving non-rectangular and various shapes of receiver mask are described.

公开(公告)号：US11894044B2

公开(公告)日：2024-02-06

申请号：US17455468

申请日：2021-11-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dean D. Gans

IPC: G11C11/4076 ,  H03K5/156

CPC classification number: G11C11/4076 ,  H03K5/1565

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for a multi-bit duty cycle monitor. A clock signal may be provided to a memory in order to synchronize one or more operations of the memory. The clock signal may have a duty cycle which is adjusted by a duty cycle adjustor of the memory. The duty cycle of the adjusted clock signal may be monitored by a multi-bit duty cycle monitor. The multi-bit duty cycle monitor may provide a multi-bit signal which indicates if the duty cycle of the adjusted clock signal is above or below a target duty cycle value (or if the duty cycle is outside tolerances around the target duty cycle). The multi-bit duty cycle monitor may provide the multi-bit signal while access operations of the memory are occurring.

公开(公告)号：US20230418471A1

公开(公告)日：2023-12-28

申请号：US18326303

申请日：2023-05-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dean D. Gans ,  Shunichi Saito

IPC: G06F3/06 ,  G06F12/10

CPC classification number: G06F3/0604 ,  G06F12/10 ,  G06F3/0673 ,  G06F3/0629 ,  G06F2212/1012

Abstract: Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.

公开(公告)号：US11568906B2

公开(公告)日：2023-01-31

申请号：US17301531

申请日：2021-04-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dean D. Gans ,  Daniel C. Skinner

IPC: G11C7/10

Abstract: Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.

公开(公告)号：US20220246186A1

公开(公告)日：2022-08-04

申请号：US17727283

申请日：2022-04-22

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Dean D. Gans ,  Sharookh Daruwalla

IPC: G11C7/22 ,  G06F13/36 ,  G11C7/10

Abstract: Methods, systems, and devices for a latency indication in a memory system or sub-system are described. An interface controller of a memory system may transmit an indication of a time delay (e.g., a wait signal) to a host in response to receiving an access command from the host. The interface controller may transmit such an indication when a latency associated with performing the access command is likely to be greater than a latency anticipated by the host. The interface controller may determine a time delay based on a status of buffer or a status of memory device, or both. The interface controller may use a pin designated and configured to transmit a command or control information to the host when transmitting a signal including an indication of a time delay. The interface controller may use a quantity, duration, or pattern of pulses to indicate a duration of a time delay.

公开(公告)号：US20220188035A1

公开(公告)日：2022-06-16

申请号：US17557818

申请日：2021-12-21

Applicant: Micron Technology, Inc.

Inventor： Dean D. Gans

IPC: G06F3/06 ,  G06F12/1009

Abstract: Methods, systems, and devices for memory with a virtual page size are described. Memory cells may be accessed in portions or page sizes that are tailored to a particular use or application. A variable page size may be defined that represents a subset or superset of memory cells in a nominal page size for the array. For example, memory cells associated with a page size of a memory array may be accessed with commands to a memory array. Each command may contain a particular addressing scheme based on the page size of the memory array and may activate one or more sets of memory cells within the array. The addressing scheme may be modified based on the page size of the memory array. Upon activating a desired set of memory cells, one or more individual activated cells may be accessed.

公开(公告)号：US11194726B2

公开(公告)日：2021-12-07

申请号：US16778151

申请日：2020-01-31

Applicant: Micron Technology, inc.

Inventor： Dean D. Gans

IPC: G06F12/0862 ,  G06F13/16 ,  H01L25/065 ,  G11C11/4093

Abstract: Methods, systems, and devices for stacked memory dice and combined access operations are described. A device may include multiple memory dice. One die may be configured as a master, and another may be configured as a slave. The master may communicate with a host device. A slave may be coupled with the master but not the host device. The device may include a first die (e.g., master) and a second die (e.g., slave). The first die may be coupled with a host device and configured to output a set of data in response to a read command. The first die may supply a first subset of the data and obtain a second subset of the data from the second die. In some cases, the first die may select, based on a data rate, a modulation scheme (e.g., PAM4, NRZ, etc.) and output the data using the selected modulation scheme.

公开(公告)号：US11152929B2

公开(公告)日：2021-10-19

申请号：US16917428

申请日：2020-06-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dean D. Gans

IPC: G11C7/22 ,  H03K5/156 ,  G11C29/50 ,  G11C11/4076 ,  G11C8/18 ,  G11C7/00 ,  G11C29/02

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for lookahead duty cycle adjustment of a clock signal. Clock signals may be provided to a semiconductor device, such as a memory device, to synchronize one or more operations. A duty cycle adjuster (DCA) of the device may adjust the clock signal(s) based on a duty code determined during an initialization of the device. While the device is in operation, a lookahead DCA (LA DCA) may test a number of different adjustments to the clock signal(s), the results of which may be determined by a duty cycle monitor (DCM). The results of the DCM may be used to select one of the tested adjustments, which may be used to update the duty code.