公开(公告)号：US11556479B1

公开(公告)日：2023-01-17

申请号：US17397799

申请日：2021-08-09

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  David Aaron Palmer

IPC: G06F12/00 ,  G06F12/0893

Abstract: Methods, systems, and devices for cache block budgeting techniques are described. In some memory systems, a controller may configure a memory device with a cache. The cache may include a first subset of blocks configured to statically operate in a first mode and a second subset of blocks configured to dynamically switch between operating in the first mode and a second mode. A block operating in the second mode may be configured to store relatively more bits per memory cell than a block operating in the first mode. The controller may track and store, for each block of the second subset of blocks, a respective ratio of cycles performed in the first mode to cycles performed in the second mode. The controller may select a block from the second subset of blocks to switch between modes responsive to a trigger and based on the respective ratio for the block.

公开(公告)号：US20220397953A1

公开(公告)日：2022-12-15

申请号：US17736886

申请日：2022-05-04

Applicant: Micron Technology, Inc.

Inventor： Junjun Wang ,  Yanming Liu ,  Deping He ,  Hua Tan

IPC: G06F1/3225 ,  G06F1/3296 ,  G06F3/06

Abstract: Methods, systems, and devices for dynamic power control are described. In some examples, a memory device may be configured to adjust a first duration for transitioning power modes. For example, the memory device may be configured to operate in a first power mode, a second power mode, and a third power mode. When operating in a second power mode, the memory device may be configured to increase or decrease the first duration for transitioning to a third power mode based on a second duration between received commands. If no commands are received during the first duration, the memory device may transition from the second power mode to the third power mode.

公开(公告)号：US11494095B1

公开(公告)日：2022-11-08

申请号：US17368579

申请日：2021-07-06

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Deping He

IPC: G06F12/00 ,  G06F3/06

Abstract: A method includes receiving, by a processing device, signaling indicative of a power cycle (PC) to a memory device (MD) having a first signal indicative of a Power On Operation and a second signal indicative of a Power Off Operation, and determining an Average Power On Time (APOT) of the MD based, at least in part, on a quantity of power cycles (n) to the MD over a predetermined time interval (PTI), and for each PC over the PTI, an amount of time between receipt of the first signal and the second signal. A sum of each of the amount of time between receipt of the first signal and the second signal in the PTI provides a total power on time (T) to the MD, and the APOT is equal to T/n. When the APOT is less than (

公开(公告)号：US20220317900A1

公开(公告)日：2022-10-06

申请号：US17725119

申请日：2022-04-20

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  David Aaron Palmer

IPC: G06F3/06

Abstract: Methods, systems, and devices for memory device with enhanced data reliability capabilities are described. For a write operation, a memory device may receive a write command from a host device indicating a first set of data. The memory device may determine to operate in first mode of operation associated with a reliability above a threshold and generate a second set of data to store with the first set of data based on operating in the first mode of operation. For a read operation, the memory device may identify that a read command received from a host device is associated with the first mode of operation. Based on operating in the first mode of operation, the memory device may select one or more reference thresholds (e.g., a subset of reference thresholds) to retrieve the first set of data and transmit the first set of data to the host device.

公开(公告)号：US11380419B1

公开(公告)日：2022-07-05

申请号：US17125503

申请日：2020-12-17

Applicant: Micron Technology, Inc.

Inventor： Jonathan Scott Parry ,  Deping He ,  Giuseppe Cariello

IPC: G11C29/50 ,  G11C29/56 ,  G11C5/14

Abstract: A memory device comprises a memory array that includes memory cells and a memory controller operatively coupled to the memory array. The memory controller includes an oscillator circuit, internal memory, a processor core coupled to the oscillator circuit and the internal memory, and configured to load operating firmware during a boot phase of the memory device, voltage detector circuitry configured to detect a decrease in a circuit supply voltage of the memory controller during the boot phase, and logic circuitry configured to halt operation of the oscillator circuit and power down the processor core and the internal memory during the boot phase in a low power mode in response to detecting the decrease in the circuit supply voltage.

公开(公告)号：US20220206689A1

公开(公告)日：2022-06-30

申请号：US17646413

申请日：2021-12-29

Applicant: Micron Technology, Inc.

Inventor： Jun Huang ,  Bhagyashree Bokade ,  Violet Gomm ,  Deping He ,  Lavanya Sriram

IPC: G06F3/06

Abstract: Methods, systems, and devices for access of a memory system based on fragmentation are described. The memory system may receive a first message indicating a set of data that the memory system is to store using a fragmentation-based write procedure. The memory system may, based on the first message, determine blocks of a memory device that satisfy a fragmentation threshold. After determining the blocks, the memory system may transmit to the host system a second message that indicates the memory system is ready to receive the set of data indicated in the first message. The memory system may then store the set of data in the determined blocks based on transmitting the second message.

公开(公告)号：US11288149B2

公开(公告)日：2022-03-29

申请号：US17065254

申请日：2020-10-07

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Giuseppe Cariello ,  Deping He ,  Scott Anthony Stoller ,  Devin Batutis ,  Preston Allen Thomson

IPC: G06F11/20 ,  G11C16/34 ,  G11C29/00 ,  G06F11/10 ,  G11C16/04

Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is provisionally removed from service in response to encountering read errors in the first memory block. Memory pages of the first memory block are tested in a second mode comprising reading memory pages at different read voltages. A raw bit error rate (RBER) or a read window budget (RWB) is determined for memory pages at the different read voltages and the provisionally removed first memory block is returned to service or retired based on the determined RBER or the RWB.

公开(公告)号：US20220057948A1

公开(公告)日：2022-02-24

申请号：US17000015

申请日：2020-08-21

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  David Aaron Palmer

IPC: G06F3/06

Abstract: Methods, systems, and devices for memory device with enhanced data reliability capabilities are described. For a write operation, a memory device may receive a write command from a host device indicating a first set of data. The memory device may determine to operate in first mode of operation associated with a reliability above a threshold and generate a second set of data to store with the first set of data based on operating in the first mode of operation. For a read operation, the memory device may identify that a read command received from a host device is associated with the first mode of operation. Based on operating in the first mode of operation, the memory device may select one or more reference thresholds (e.g., a subset of reference thresholds) to retrieve the first set of data and transmit the first set of data to the host device.

公开(公告)号：US20210382769A1

公开(公告)日：2021-12-09

申请号：US16891615

申请日：2020-06-03

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Jonathan S. Parry ,  Giuseppe Cariello ,  Deping He

IPC: G06F11/07 ,  G06F11/30

Abstract: Techniques for access operation status signaling for memory systems are described. In some examples, a memory system may respond to access commands from a host system by performing access operations such as read or write operations. In accordance with examples as disclosed herein, a system may be configured to support access operation status signaling between a host system and a memory system, which may improve the ability of the system to adapt to various access scenarios, including when access operation completion is delayed. For example, when a memory system is performing an error recovery or media management operation, the memory system may indicate that the error recovery or media management operation is being performed or is otherwise ongoing. Such status signaling may indicate that the memory system is actively performing operations, which may be used to inhibit a reset or reinitialization by a host system.

公开(公告)号：US20210019241A1

公开(公告)日：2021-01-21

申请号：US17065254

申请日：2020-10-07

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Giuseppe Cariello ,  Deping He ,  Scott Anthony Stoller ,  Devin Batutis ,  Preston Allen Thomson

IPC: G06F11/20 ,  G11C16/34 ,  G11C29/00 ,  G06F11/10

Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is provisionally removed from service in response to encountering read errors in the first memory block. Memory pages of the first memory block are tested in a second mode comprising reading memory pages at different read voltages. A raw bit error rate (RBER) or a read window budget (RWB) is determined for memory pages at the different read voltages and the provisionally removed first memory block is returned to service or retired based on the determined RBER or the RWB.