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    Managed memory systems with multiple priority queues
    61.
    发明授权
    Managed memory systems with multiple priority queues 有权

    公开(公告)号：US12299331B2

    公开(公告)日：2025-05-13

    申请号：US18583540

    申请日：2024-02-21

    Applicant: Micron Technology, Inc.

    Inventor： Nicola Del Gatto ,  Massimiliano Patriarca ,  Antonino Caprì ,  Emanuele Confalonieri ,  Angelo Alberto Rovelli

    IPC: G06F3/06

    Abstract: Methods, systems, and devices for managed memory systems with multiple priority queues are described. Memory access commands may be received from a host and stored in a command queue. First and second subsets of the commands, respectively associated with first and second priorities, may be determined. The first and second subsets may be routed from the command queue to first and second queues, respectively. The first and second subsets may be processed from the first and second queues to third and fourth queues, respectively, at a storage controller, according to first and second processes that may be run concurrently according to parameters for prioritization between the first and second priorities. Data associated with the commands may be received from the host, temporarily stored in a buffer, then moved to a storage memory (for write commands) or retrieved from the storage memory, temporarily stored in the buffer, then transmitted to the host (for read commands).

    DYNAMIC PAGE MAPPING WITH COMPRESSION
    62.
    发明申请
    DYNAMIC PAGE MAPPING WITH COMPRESSION 有权

    公开(公告)号：US20250094343A1

    公开(公告)日：2025-03-20

    申请号：US18782147

    申请日：2024-07-24

    Applicant: Micron Technology, Inc.

    Inventor： Rishabh Dubey ,  Marco Sforzin ,  Emanuele Confalonieri ,  Danilo Caraccio ,  Daniele Balluchi ,  Nicola Del Gatto

    IPC: G06F12/02 ,  G06F13/16

    Abstract: A variety of applications can include a memory device having dynamic page mapping with compression. The memory device can include a mapping table having an entry location to associate a virtual page with a physical address of a first stripe of data of the virtual page. The entry location can include a flag along with the physical address of the first stripe. The flag can identify data of the virtual page as being compressed or uncompressed. A controller of the memory device, responsive to the flag identifying the data of virtual page being compressed, is structured to generate a format of compressed data of the first stripe with a header. The header can include a count of additional physical addresses to store compressed data of the virtual page and the additional physical addresses. Additional apparatus, systems, and methods are disclosed.

    MEMORY CONTROLLER FOR MANAGING RAID INFORMATION
    64.
    发明申请
    MEMORY CONTROLLER FOR MANAGING RAID INFORMATION 有权

    公开(公告)号：US20240427526A1

    公开(公告)日：2024-12-26

    申请号：US18830096

    申请日：2024-09-10

    Applicant: Micron Technology, Inc.

    Inventor： Nicola Del Gatto ,  Emanuele Confalonieri ,  Paolo Amato ,  Patrick Estep ,  Stephen S. Pawlowski

    IPC: G06F3/06 ,  G06F12/0864

    Abstract: A memory controller can include a front end portion configured to interface with a host, a central controller portion configured to manage data, a back end portion configured to interface with memory devices. The memory controller can include interface management circuitry coupled to a cache and a memory device. The memory controller can receive, by the interface management controller, a first signal indicative of data associated with a memory access request from a host. The memory controller can transmit a second signal indicative of the data to cache the data in a first location in the cache. The memory controller can transmit a third signal indicative of the data to cache the data in a second location in the cache.

    Read Data Path for a Memory System
    67.
    发明公开
    Read Data Path for a Memory System 审中-公开

    公开(公告)号：US20240070024A1

    公开(公告)日：2024-02-29

    申请号：US17823476

    申请日：2022-08-30

    Applicant: Micron Technology, Inc.

    Inventor： Nicola Del Gatto ,  Emanuele Confalonieri

    IPC: G06F11/10 ,  G06F11/00

    CPC classification number: G06F11/1076 ,  G06F11/008

    Abstract: Described apparatuses and methods relate to a read data path for a memory system. A memory system can include logic that receives data from a memory. The data may include first data, parity data, and metadata that enables a reliability check of the data. The logic may perform the reliability check of the data to determine an accuracy of the data. If the data is determined not to include an error, the data may be transmitted for accessing by a requestor. If the data is determined to include an error, however, a data recovery process may be initiated to recover the corrupted data along a separate data path. In doing so, the apparatuses and methods related to a read data path for a memory system and described herein may reduce the likelihood that a memory system returns corrupted data to a requestor.

    Managed memory systems with multiple priority queues
    68.
    发明授权
    Managed memory systems with multiple priority queues 有权

    公开(公告)号：US11914893B2

    公开(公告)日：2024-02-27

    申请号：US16951985

    申请日：2020-11-18

    Applicant: Micron Technology, Inc.

    Inventor： Nicola Del Gatto ,  Massimiliano Patriarca ,  Antonino Caprì ,  Emanuele Confalonieri ,  Angelo Alberto Rovelli

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0635 ,  G06F3/0656 ,  G06F3/0679

    Abstract: Methods, systems, and devices for managed memory systems with multiple priority queues are described. Memory access commands may be received from a host and stored in a command queue. First and second subsets of the commands, respectively associated with first and second priorities, may be determined. The first and second subsets may be routed from the command queue to first and second queues, respectively. The first and second subsets may be processed from the first and second queues to third and fourth queues, respectively, at a storage controller, according to first and second processes that may be run concurrently according to parameters for prioritization between the first and second priorities. Data associated with the commands may be received from the host, temporarily stored in a buffer, then moved to a storage memory (for write commands) or retrieved from the storage memory, temporarily stored in the buffer, then transmitted to the host (for read commands).

    MEMORY CONTROLLER ARCHITECTURE
    70.
    发明公开
    MEMORY CONTROLLER ARCHITECTURE 审中-公开

    公开(公告)号：US20240004799A1

    公开(公告)日：2024-01-04

    申请号：US18202802

    申请日：2023-05-26

    Applicant: Micron Technology, Inc.

    Inventor： Emanuele Confalonieri ,  Stephen S. Pawlowski ,  Patrick Estep

    IPC: G06F12/0897 ,  G06F11/10

    CPC classification number: G06F12/0897 ,  G06F11/1064 ,  G06F2212/1032

    Abstract: An apparatus can include a plurality of memory devices and a memory controller coupled to the plurality of memory devices via a plurality of memory channels. The plurality of memory channels are organized as a plurality of channel groups. The memory controller comprises a plurality of memory access request/response buffer sets, and each memory access request/response buffer set of the plurality of memory access request/response buffer sets corresponds to a different one of the plurality of channel groups.

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