公开(公告)号：US20200278736A1

公开(公告)日：2020-09-03

申请号：US16290181

申请日：2019-03-01

Applicant: Micron Technology, Inc.

Inventor： Frank F. Ross ,  Matthew A. Prather

IPC: G06F1/3234 ,  G11C5/14 ,  G06F3/06

Abstract: The present disclosure includes apparatuses and methods related to power management in memory. Memory devices with multiple input/output ports may have the ports separately managed to transfer data from the various to a host or other components of the module based on certain power management signaling or constraints. For example, a memory device with multiple ports may be managed to transfer data to a host from one set of ports in response to power management (or other) signaling, and the device may be managed to transfer other data to another memory device in response to different power management (or other signaling). Power management may be done onboard a memory module with or without direction from a host. Power management may be performed by a dedicated integrated circuit. Data may be transferred from or between different classes of memory devices, using different ports, based on power management, e.g., criteria.

公开(公告)号：US20200234753A1

公开(公告)日：2020-07-23

申请号：US16838473

申请日：2020-04-02

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather ,  Thomas H. Kinsley

IPC: G11C11/4074 ,  G06F13/10

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems in which a memory device can include a voltage regulator for adjusting a supply voltage to an output voltage and providing the output voltage to other devices external to the memory device (e.g., other memory devices in the same memory system, processors, graphics chipsets, other logic circuits, expansion cards, etc.). A memory device may comprise one or more external inputs configured to receive a supply voltage having a first voltage level; a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage having a second voltage level different from the first voltage level; one or more memories configured to receive the output voltage from the voltage regulator; and one or more external outputs configured to supply the output voltage to one or more connected devices.

公开(公告)号：US20200210278A1

公开(公告)日：2020-07-02

申请号：US16237147

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： Randall J. Rooney ,  Matthew A. Prather

IPC: G06F11/10 ,  G11C29/42 ,  G11C29/44 ,  G11C11/406

Abstract: Methods, systems, and apparatuses for memory (e.g., DRAM) having an error check and scrub (ECS) procedure in conjunction with refresh operations are described. While a refresh operation reads the code words of a memory row, ECS procedures may be performed on some of the sensed code words. When the write portion of the refresh begins, a code word discovered to have errors may be corrected before it is written back to the memory row. The ECS procedure can be incremental across refresh operations, beginning, for example, each ECS at the code word where the pervious ECS for that row left off. The ECS procedure can include an out-of-order (OOO) procedure where ECS is performed more often for certain identified code words.

公开(公告)号：US10665288B2

公开(公告)日：2020-05-26

申请号：US16109520

申请日：2018-08-22

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather ,  Thomas H. Kinsley

IPC: G11C11/4074 ,  G06F13/10 ,  G06F1/26 ,  H02M3/156

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems in which a memory device can include a voltage regulator for adjusting a supply voltage to an output voltage and providing the output voltage to other devices external to the memory device (e.g., other memory devices in the same memory system, processors, graphics chipsets, other logic circuits, expansion cards, etc.). A memory device may comprise one or more external inputs configured to receive a supply voltage having a first voltage level; a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage having a second voltage level different from the first voltage level; one or more memories configured to receive the output voltage from the voltage regulator; and one or more external outputs configured to supply the output voltage to one or more connected devices.

公开(公告)号：US10657081B2

公开(公告)日：2020-05-19

申请号：US16014498

申请日：2018-06-21

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Matthew A. Prather

IPC: G11C5/14 ,  G06F13/16 ,  G06F5/06 ,  G06F1/3296 ,  G06F1/3234 ,  G06F1/3206

Abstract: Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.

公开(公告)号：US10656878B2

公开(公告)日：2020-05-19

申请号：US15841126

申请日：2017-12-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew A. Prather

IPC: G06F3/06 ,  G06F12/02 ,  G06F13/16

Abstract: Apparatuses, hybrid memory modules, memories, and methods for configuring I/Os of a memory for a hybrid memory module are described. An example apparatus includes a non-volatile memory, a control circuit coupled to the non-volatile memory, and a volatile memory coupled to the control circuit. The volatile memory is configured to enable a first subset of I/Os for communication with a bus and enable a second subset of I/O for communication with the control circuit, wherein the control circuit is configured to transfer information between the volatile memory and the non-volatile memory.

公开(公告)号：US10424356B2

公开(公告)日：2019-09-24

申请号：US16047954

申请日：2018-07-27

Applicant: Micron Technology, Inc.

Inventor： Gary Howe ,  Eric J. Stave ,  Thomas H. Kinsley ,  Matthew A. Prather

IPC: G11C7/22 ,  G11C7/10 ,  G06F13/40 ,  G11C8/10

Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.

公开(公告)号：US10395721B1

公开(公告)日：2019-08-27

申请号：US16109499

申请日：2018-08-22

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather ,  Thomas H. Kinsley

IPC: G11C11/4074 ,  G06F13/10 ,  H02M3/156 ,  G06F1/26

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems in which a memory device can include a voltage regulator for adjusting a supply voltage to an output voltage and providing the output voltage to other devices external to the memory device (e.g., other memory devices in the same memory system, processors, graphics chipsets, other logic circuits, expansion cards, etc.). A memory device may comprise one or more external inputs configured to receive a supply voltage having a first voltage level; a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage having a second voltage level different from the first voltage level; one or more memories configured to receive the output voltage from the voltage regulator; and one or more external outputs configured to supply the output voltage to one or more connected devices.

公开(公告)号：US10282133B2

公开(公告)日：2019-05-07

申请号：US15693095

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather

IPC: G06F12/00 ,  G06F3/06

Abstract: A memory device is provided. The memory device includes a memory array, operation circuitry configured to perform a memory operation in the memory array in response to a command received from a connected host device, and delay circuitry configured to delay the performance of the memory operation in response to one or more bits received with the command. The one or more bits indicate a duration by which to delay the performance of the memory operation.

公开(公告)号：US20190065416A1

公开(公告)日：2019-02-28

申请号：US16014498

申请日：2018-06-21

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Matthew A. Prather

IPC: G06F13/16 ,  G06F1/32 ,  G06F5/06

Abstract: Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.