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    METHODS AND SYSTEMS FOR CREATING NETWORKS
    63.
    发明申请
    METHODS AND SYSTEMS FOR CREATING NETWORKS 审中-公开

    公开(公告)号：US20170098154A1

    公开(公告)日：2017-04-06

    申请号：US15286202

    申请日：2016-10-05

    Applicant: Micron Technology, Inc.

    Inventor： Paul Glendenning ,  Michael C. Leventhal ,  Paul Dlugosch ,  Harold B Noyes

    IPC: G06N3/06 ,  G06F17/30 ,  G06F3/0481 ,  G06N3/10

    Abstract: The Automata Processor Workbench (AP Workbench) is an application for creating and editing designs of AP networks (e.g., one or more portions of the state machine engine, one or more portions of the FSM lattice, or the like) based on, for example, an Automata Network Markup Language (ANML). For instance, the application may include a tangible, non-transitory computer-readable medium configured to store instructions executable by a processor of an electronic device, wherein the instructions include instructions to represent an automata network as a graph.

    Unrolling quantifications to control in-degree and/or out-degree of automaton
    64.
    发明授权
    Unrolling quantifications to control in-degree and/or out-degree of automaton 有权
    展开量化以控制自动机的程度和/或程度

    公开(公告)号：US09298437B2

    公开(公告)日：2016-03-29

    申请号：US14252600

    申请日：2014-04-14

    Applicant: Micron Technology, Inc.

    Inventor： Junjuan Xu ,  Paul Glendenning

    IPC: G06F9/45 ,  G06F9/44 ,  G06F17/50

    CPC classification number: G06F8/45 ,  G06F8/447 ,  G06F9/4498 ,  G06F17/5054

    Abstract: Apparatus, systems, and methods for a compiler are disclosed. One such compiler parses a human readable expression into a syntax tree and converts the syntax tree into an automaton having in-transitions and out-transitions. Converting can include unrolling the quantification as a function of in-degree limitations wherein in-degree limitations includes a limit on the number of transitions into a state of the automaton. The compiler can also convert the automaton into an image for programming a parallel machine, and publishes the image. Additional apparatus, systems, and methods are disclosed.

    Abstract translation: 公开了用于编译器的装置，系统和方法。 一个这样的编译器将可读的表达式解析成语法树，并将语法树转换成具有转换和转出的自动机。 转换可以包括作为度数限制的函数展开量化，其中度数限制包括对自动机状态的转换次数的限制。 编译器还可以将自动机转换成用于编程并行机的映像，并发布映像。 公开了附加装置，系统和方法。

    State grouping for element utilization
    65.
    发明授权
    State grouping for element utilization 有权
    元素利用的状态分组

    公开(公告)号：US09104828B2

    公开(公告)日：2015-08-11

    申请号：US14335537

    申请日：2014-07-18

    Applicant: Micron Technology, Inc.

    Inventor： Junjuan Xu ,  Paul Glendenning

    IPC: G06F17/50 ,  G06F9/45 ,  G06F9/44

    CPC classification number: G06F17/505 ,  G06F8/447 ,  G06F9/4498 ,  G06F17/5054

    Abstract: Embodiments of a system and method for generating an image configured to program a parallel machine from source code are disclosed. One such parallel machine includes a plurality of state machine elements (SMEs) grouped into pairs, such that SMEs in a pair have a common output. One such method includes converting source code into an automaton comprising a plurality of interconnected states, and converting the automaton into a netlist comprising instances corresponding to states in the automaton, wherein converting includes pairing states corresponding to pairs of SMEs based on the fact that SMEs in a pair have a common output. The netlist can be converted into the image and published.

    Abstract translation: 公开了一种用于生成被配置为从源代码编程并行机器的图像的系统和方法的实施例。 一个这样的并行机器包括分组成对的多个状态机元件（SME），使得一对中的SME具有公共输出。 一种这样的方法包括将源代码转换成包括多个互连状态的自动机，并将自动机转换成包括对应于自动机中的状态的实例的网表，其中转换包括对应于中小企业对的配对状态，基于以下事实： 一对有一个共同的输出。 网表可以转换为图像并发布。

    Counter operation in a state machine lattice
    66.
    发明授权
    Counter operation in a state machine lattice 有权
    在状态机格子中的计数器操作

    公开(公告)号：US09058465B2

    公开(公告)日：2015-06-16

    申请号：US14143398

    申请日：2013-12-30

    Applicant: Micron Technology, Inc.

    Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning

    IPC: G06F7/38 ,  G06F7/00 ,  H01L25/00 ,  G05B19/045 ,  G06F15/82 ,  G06F21/56 ,  G06N5/04

    CPC classification number: G05B19/045 ,  G06F9/4498 ,  G06F15/82 ,  G06F21/567 ,  G06F2207/025 ,  G06N5/047 ,  H03K19/17724 ,  H03K19/17748

    Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting a number of times a programmable element in the lattice detects a condition. The counter may be configured to output in response to counting the condition was detected a certain number of times. For example, the counter may be configured to output in response to determining a condition was detected at least (or no more than) the certain number of times, determining the condition was detected exactly the certain number of times, or determining the condition was detected within a certain range of times. The counter may be coupled to other counters in the device for determining high-count operations and/or certain quantifiers.

    Abstract translation: 公开了方法和装置，其中包括有限状态机格的装置。 格子可以包括适合于对格子中的可编程元件检测到条件的次数进行计数的计数器。 计数器可以配置为响应于计数而输出，条件被检测到一定次数。 例如，计数器可以被配置为响应于确定至少（或不多于）一定次数检测到的条件而输出，确定条件被精确地检测到一定次数，或者确定检测到条件 在一定的时间范围内。 计数器可以耦合到设备中的其他计数器，用于确定高计数操作和/或某些量化器。

    METHOD AND APPARATUS FOR COMPILING REGULAR EXPRESSIONS
    67.
    发明申请
    METHOD AND APPARATUS FOR COMPILING REGULAR EXPRESSIONS 有权
    用于编译常规表达的方法和装置

    公开(公告)号：US20140229925A1

    公开(公告)日：2014-08-14

    申请号：US14252542

    申请日：2014-04-14

    Applicant: Micron Technology, Inc.

    Inventor： Paul Glendenning ,  Junjuan Xu

    IPC: G06F9/45

    CPC classification number: G06F8/41 ,  G06F8/427 ,  G06F8/443 ,  G06F8/447 ,  G06F9/4498 ,  G06F17/5045 ,  G06F17/5054

    Abstract: Apparatus, systems, and methods for a compiler are described. One such compiler converts source code into an automaton comprising states and transitions between the states, wherein the states in the automaton include a special purpose state that corresponds to a special purpose hardware element. The compiler converts the automaton into a netlist, and places and routes the netlist to provide machine code for configuring a target device.

    Abstract translation: 描述了编译器的装置，系统和方法。 一个这样的编译器将源代码转换成包括状态之间的状态和转换的自动机，其中自动机中的状态包括对应于专用硬件元件的专用状态。 编译器将自动机转换为网表，并放置和路由网表以提供用于配置目标设备的机器代码。

    BOOLEAN LOGIC IN A STATE MACHINE LATTICE
    68.
    发明申请
    BOOLEAN LOGIC IN A STATE MACHINE LATTICE 有权
    BOOLEAN逻辑在一个状态机床

    公开(公告)号：US20140077838A1

    公开(公告)日：2014-03-20

    申请号：US14087973

    申请日：2013-11-22

    Applicant: Micron Technology, Inc.

    Inventor： Harold B. Noyes ,  David R. Brown ,  Paul Glendenning ,  Irene Junjuan Xu

    IPC: H03K19/20

    CPC classification number: H03K19/17708 ,  G05B19/045 ,  G06F7/00 ,  G06F9/4498 ,  G06F17/5054 ,  H03K19/0175 ,  H03K19/17704 ,  H03K19/20 ,  H03K19/21 ,  Y02T10/82

    Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.

    Abstract translation: 公开了方法和装置，其中包括有限状态机格的装置。 晶格可以包括可编程布尔逻辑单元，其可以被编程为在数据流上执行各种逻辑功能。 可编程性包括对布尔逻辑单元的第一输入的反转，布尔逻辑单元的最后输出的反转，以及选择与门或或门作为布尔逻辑单元的最终输出。 布尔逻辑单元还包括数据电路的结尾，该数据电路被配置为仅在布尔逻辑单元接收到表示数据流结束的数据结束后才输出布尔逻辑单元。

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