公开(公告)号：US20050251668A1

公开(公告)日：2005-11-10

申请号：US11103912

申请日：2005-04-11

申请人： Shailender Chaudhry ,  Marc Tremblay ,  Paul Caprioli

发明人： Shailender Chaudhry ,  Marc Tremblay ,  Paul Caprioli

IPC分类号： G06F9/00 ,  G06F9/38

CPC分类号： G06F9/3863 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3865

摘要： One embodiment of the present invention provides a system that facilitates deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order. During a normal execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint that can subsequently be used to return execution of the program to the point of the instruction. Next, the system executes the instruction and subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order. Upon encountering a store during the execute-ahead mode, the system determines if the store buffer is full. If so, the system prefetches a cache line for the store, and defers execution of the store. If the number of stores that are encountered during execute-ahead mode exceeds the capacity of the store buffer, which means that the store buffer will never have additional space to accept additional stores during the execute-ahead mode because the store buffer is gated, the system directly enters the scout mode, without waiting for the deferred queue to eventually fill.

摘要翻译： 本发明的一个实施例提供了一种系统，其有助于在按照程序顺序执行时，推迟执行具有未解决的数据依赖性的指令。 在正常执行模式下，系统以程序顺序发出执行指令。 在执行指令期间遇到未解决的数据依赖性时，系统产生一个检查点，随后可以使用该检查点将程序的执行返回到指令点。 接下来，系统以执行模式执行指令和后续指令，其中由于未解决的数据依赖性而不能执行的指令被延迟，并且其中以程序顺序执行其他非延迟指令。 在执行提前模式期间遇到存储器时，系统确定存储缓冲区是否已满。 如果是这样，系统将预取商店的高速缓存线，并延迟商店的执行。 如果在执行超前模式期间遇到的存储的数量超过了存储缓冲区的容量，这意味着由于存储缓冲区被选通，在执行提前模式下，存储缓冲区将永远不会有额外的空间来接受附加存储， 系统直接进入侦察模式，无需等待延期队列最终填满。

公开(公告)号：US06704841B2

公开(公告)日：2004-03-09

申请号：US10186091

申请日：2002-06-26

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F1200

CPC分类号： G06F9/3834 ,  G06F9/383 ,  G06F9/3842 ,  G06F9/3861 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0855 ,  G06F2212/507

摘要： One embodiment of the present invention provides a system for facilitating speculative store operations in a multiprocessor system. This system operates by maintaining a record of speculative store operations that are in process at an L2 cache in the multiprocessor system, wherein a speculative store operation is a store operation that is speculatively executed before a preceding store operation has returned. Upon receiving a load operation at the L2 cache from an L1 cache, the system examines the record of speculative store operations to determine if there exists a matching speculative store operation that is directed to the same location that the load operation is directed to. If so, the system ensures that the load operation takes place after the matching speculative store operation completes.

摘要翻译： 本发明的一个实施例提供一种用于促进多处理器系统中的推测存储操作的系统。 该系统通过维持在多处理器系统中的L2高速缓存处理中的推测存储操作的记录来进行操作，其中推测存储操作是在先前的存储操作返回之前被推测地执行的存储操作。 在从L1高速缓存接收到L2高速缓存的加载操作时，系统检查推测存储操作的记录，以确定是否存在针对加载操作指向的相同位置的匹配推测存储操作。 如果是这样，系统确保在匹配推测存储操作完成后进行加载操作。

公开(公告)号：US06701417B2

公开(公告)日：2004-03-02

申请号：US10061493

申请日：2002-01-31

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F1208

CPC分类号： G06F12/0808 ,  G06F12/0811 ,  G06F12/0831

摘要： One embodiment of the present invention provides a multiprocessor system that supports multiple cache line invalidations within the same cycle. This multiprocessor system includes a plurality of processors and a lower-level cache that is configured to support multiple concurrent operations. It also includes a plurality of higher-level caches coupled to the plurality of processors, wherein a given higher-level cache is configured to support multiple concurrent invalidations of lines within the given higher-level cache. In one embodiment of the present invention, the lower-level cache includes a plurality of banks that can be accessed in parallel to support multiple concurrent operations. In a variation on this embodiment, each line in a given higher-level cache includes a valid bit that can be used to invalidate the line. These valid bits are contained in a memory that is organized into a plurality of banks that are associated with the plurality of banks of the lower-level cache.

摘要翻译： 本发明的一个实施例提供一种在同一周期内支持多个高速缓存行无效的多处理器系统。 该多处理器系统包括多个处理器和被配置为支持多个并发操作的下级缓存。 它还包括耦合到多个处理器的多个较高级别的高速缓存，其中给定的较高级别的高速缓存被配置为支持给定的较高级别高速缓存中的线路的多个并发的无效。 在本发明的一个实施例中，下级缓存包括可以并行访问以支持多个并发操作的多个存储体。 在该实施例的变型中，给定的较高级别高速缓存中的每一行包括可用于使线路无效的有效位。 这些有效位包含在被组织成与下级高速缓存的多个存储体相关联的多个存储体的存储器中。

公开(公告)号：US06684398B2

公开(公告)日：2004-01-27

申请号：US09761326

申请日：2001-01-16

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F900

CPC分类号： G06F9/3851 ,  G06F9/3842

摘要： One embodiment of the present invention provides a system that facilitates entering and exiting a critical section of code for a speculative thread. The system supports a head thread that executes program instructions, and the speculative thread that speculatively executes program instructions in advance of the head thread. During an entry into the critical section by the speculative thread, the system increments a variable containing a number of virtual locks held by the speculative thread. Note that a virtual lock held by the speculative thread is associated with the critical section and is used to keep track of the fact that the speculative thread has entered the critical section. Also note that this virtual lock does not prevent the speculative thread or other threads from entering the critical section. During an exit from the critical section by the speculative thread, the system decrements the variable containing the number of virtual locks held by the speculative thread. The speculative eventually receives a request to perform a join operation with the head thread to merge state associated with the speculative thread into state associated with the head thread. Upon receiving this request, the speculative thread waits to perform the join operation until the variable containing the number of virtual locks held by the speculative thread equals zero. In one embodiment of the present invention, the system additionally waits to perform the join operation until no virtual locks in a list of virtual locks accessed by the speculative thread are held by the other head threads.

摘要翻译： 本发明的一个实施例提供一种便于进入和退出用于推测线程的关键代码段的系统。 该系统支持执行程序指令的头部线程，以及在头部线程之前推测性地执行程序指令的推测线程。 在通过推测线程进入关键部分期间，系统会增加包含推测线程所持有的多个虚拟锁的变量。 请注意，由推测线程保持的虚拟锁与关键部分相关联，并用于跟踪推测线程已进入关键部分的事实。 还要注意，这个虚拟锁并不能阻止投机线程或其他线程进入临界区。 在通过推测线程从关键部分退出之前，系统递减包含推测线程所持有的虚拟锁数的变量。 推测最终接收到执行与头线程的连接操作的请求，以将与推测线程相关联的状态合并到与头线程相关联的状态。 在接收到该请求之后，推测线程等待执行连接操作，直到包含推测线程所持有的虚拟锁数的变量等于零为止。 在本发明的一个实施例中，系统另外等待执行连接操作，直到由推测线程访问的虚拟锁列表中的虚拟锁由其他头部线程保持为止。

公开(公告)号：US06681318B2

公开(公告)日：2004-01-20

申请号：US09761216

申请日：2001-01-16

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F938

CPC分类号： G06F9/3802 ,  G06F9/3808 ,  G06F9/3879

摘要： One embodiment of the present invention provides a system that prefetches instructions by using an assist processor to perform prefetch operations in advance of a primary processor. The system operates by executing executable code on the primary processor, and simultaneously executing a reduced version of the executable code on the assist processor. This reduced version of the executable code executes more quickly than the executable code, and performs prefetch operations for the primary processor in advance of when the primary processor requires the instructions. The system also stores the prefetched instructions into a cache that is accessible by the primary processor so that the primary processor is able to access the prefetched instructions without having to retrieve the prefetched instructions from a main memory. In one embodiment of the present invention, prior to executing the executable code, the system compiles source code into executable code for the primary processor. Next, the system profiles the executable code to create instruction traces for frequently referenced portions of the executable code. The system then produces the reduced version of the executable code for the assist processor by producing prefetch instructions to prefetch portions of the instruction traces into a cache that is accessible by the primary processor. The system also inserts communication instructions into the executable code for the primary processor and into the reduced version of the executable code for the assist processor to transfer progress information from the primary processor to the assist processor. This progress information triggers the assist processor to perform the prefetch operations.

摘要翻译： 本发明的一个实施例提供一种通过使用辅助处理器在主处理器之前执行预取操作来预取指令的系统。 该系统通过在主处理器上执行可执行代码来操作，并且在辅助处理器上同时执行可执行代码的简化版本。 该可执行代码的这种缩减版本比可执行代码执行得更快，并且在主处理器需要指令之前，对主处理器执行预取操作。 该系统还将预取指令存储到可由主处理器访问的高速缓存中，使得主处理器能够访问预取指令，而不必从主存储器检索预取指令。 在本发明的一个实施例中，在执行可执行代码之前，系统将源代码编译成主处理器的可执行代码。 接下来，系统配置可执行代码以为可执行代码的经常被引用的部分创建指令轨迹。 该系统然后通过产生预取指令来产生用于辅助处理器的可执行代码的简化版本，以将指令迹线的部分预取到可由主处理器访问的高速缓存中。 系统还将通信指令插入用于主处理器的可执行代码中，并将辅助处理器的执行代码的缩减版本插入到主处理器中的进程信息到辅助处理器。 该进度信息触发辅助处理器执行预取操作。

公开(公告)号：US08898436B2

公开(公告)日：2014-11-25

申请号：US12426550

申请日：2009-04-20

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30098 ,  G06F9/30112 ,  G06F9/30138 ,  G06F9/3838 ,  G06F9/384

摘要： A register file, in a processor, includes a first plurality of registers of a first size, n-bits. A decoder uses a mapping that divides the register file into a second plurality M of registers having a second size. Each of the registers having the second size is assigned a different name in a continuous name space. Each register of the second size includes a plurality N of registers of the first size, n-bits. Each register in the plurality N of registers is assigned the same name as the register of the second size that includes that plurality. State information is maintained in the register file for each n-bit register. The dependence of an instruction on other instructions is detected through the continuous name space. The state information allows the processor to determine when the information in any portion, or all, of a register is valid.

摘要翻译： 在处理器中的寄存器文件包括第一大小的n位的第一多个寄存器。 解码器使用将寄存器文件分成具有第二大小的第二多个寄存器M的映射。 具有第二大小的每个寄存器在连续的名称空间中被分配不同的名称。 第二大小的每个寄存器包括多个N个第一大小的寄存器，n位。 多个N个寄存器中的每个寄存器被分配与包括该多个寄存器的第二大小的寄存器相同的名称。 状态信息保存在每个n位寄存器的寄存器文件中。 通过连续名称空间检测指令对其他指令的依赖性。 状态信息允许处理器确定寄存器的任何部分或全部中的信息何时有效。

公开(公告)号：US07484080B2

公开(公告)日：2009-01-27

申请号：US11103912

申请日：2005-04-11

申请人： Shailender Chaudhry ,  Marc Tremblay ,  Paul Caprioli

发明人： Shailender Chaudhry ,  Marc Tremblay ,  Paul Caprioli

IPC分类号： G06F9/00

CPC分类号： G06F9/3863 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3865

摘要： One embodiment of the present invention provides a system that facilitates deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order. During a normal execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint that can subsequently be used to return execution of the program to the point of the instruction. Next, the system executes the instruction and subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order. Upon encountering a store during the execute-ahead mode, the system determines if the store buffer is full. If so, the system prefetches a cache line for the store, and defers execution of the store. If the number of stores that are encountered during execute-ahead mode exceeds the capacity of the store buffer, which means that the store buffer will never have additional space to accept additional stores during the execute-ahead mode because the store buffer is gated, the system directly enters the scout mode, without waiting for the deferred queue to eventually fill.

摘要翻译： 本发明的一个实施例提供了一种系统，其有助于在按照程序顺序执行时，推迟执行具有未解决的数据依赖性的指令。 在正常执行模式下，系统以程序顺序发出执行指令。 在执行指令期间遇到未解决的数据依赖性时，系统产生一个检查点，随后可以使用该检查点将程序的执行返回到指令点。 接下来，系统以执行模式执行指令和后续指令，其中由于未解决的数据依赖性而不能执行的指令被延迟，并且其中以程序顺序执行其他非延迟指令。 在执行提前模式期间遇到存储器时，系统确定存储缓冲区是否已满。 如果是这样，系统将预取商店的高速缓存线，并延迟商店的执行。 如果在执行超前模式期间遇到的存储的数量超过了存储缓冲区的容量，这意味着由于存储缓冲区被选通，在执行提前模式下，存储缓冲区将永远不会有额外的空间来接受附加存储， 系统直接进入侦察模式，无需等待延期队列最终填满。

公开(公告)号：US20080189531A1

公开(公告)日：2008-08-07

申请号：US11703462

申请日：2007-02-06

申请人： Shailender Chaudhry ,  Paul Caprioli ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Paul Caprioli ,  Marc Tremblay

IPC分类号： G06F9/44

CPC分类号： G06F9/30181 ,  G06F9/30189 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3863

摘要： One embodiment of the present invention provides a system that prevents data hazards during simultaneous speculative threading. The system starts by executing instructions in an execute-ahead mode using a first thread. While executing instructions in the execute-ahead mode, the system maintains dependency information for each register indicating whether the register is subject to an unresolved data dependency. Upon the resolution of a data dependency during execute-ahead mode, the system copies dependency information to a speculative copy of the dependency information. The system then commences execution of the deferred instructions in a deferred mode using a second thread. While executing instructions in the deferred mode, if the speculative copy of the dependency information for a destination register indicates that a write-after-write (WAW) hazard exists with a subsequent non-deferred instruction executed by the first thread in execute-ahead mode, the system uses the second thread to execute the deferred instruction to produce a result and forwards the result to be used by subsequent deferred instructions without committing the result to the architectural state of the destination register. Hence, the system makes the result available to the subsequent deferred instructions without overwriting the result produced by a following non-deferred instruction.

摘要翻译： 本发明的一个实施例提供一种在同时推测的线程中防止数据危害的系统。 系统通过使用第一个线程以执行模式执行指令来启动。 在执行执行模式下执行指令时，系统维护每个寄存器的依赖信息，指示寄存器是否受到未解析的数据依赖。 在执行提前模式下解析数据依赖关系时，系统将依赖关系信息复制到依赖关系信息的推测性副本。 然后，系统使用第二个线程以延迟模式开始执行延迟指令。 在延迟模式下执行指令时，如果目的寄存器的依赖关系信息的推测性副本指示在执行提前模式下由第一线程执行的后续非延迟指令存在写后写入（WAW）危险 ，系统使用第二个线程执行延迟指令以产生结果，并转发后续延迟指令使用的结果，而不将结果提交到目标寄存器的体系结构状态。 因此，系统使结果可用于后续延期指令，而不会覆盖由以下非延迟指令产生的结果。

公开(公告)号：US20070271445A1

公开(公告)日：2007-11-22

申请号：US11832777

申请日：2007-08-02

申请人： Marc Tremblay ,  Quinn Jacobson ,  Shailender Chaudhry

发明人： Marc Tremblay ,  Quinn Jacobson ,  Shailender Chaudhry

IPC分类号： G06F9/30

CPC分类号： G06F12/0862 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/467 ,  G06F12/0815

摘要： One embodiment of the present invention provides a system that selectively monitors store instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processor until the transactional execution successfully completes. Upon encountering a store instruction during transactional execution of a block of instructions, the system determines whether the store instruction is a monitored store instruction or an unmonitored store instruction. If the store instruction is a monitored store instruction, the system performs the store operation, and store-marks a cache line associated with the store instruction to facilitate subsequent detection of an interfering data access to the cache line from another process. If the store instruction is an unmonitored store instruction, the system performs the store operation without store-marking the cache line.

摘要翻译： 本发明的一个实施例提供了一种系统，其选择性地监视存储指令以支持进程的事务性执行，其中在事务执行期间进行的改变不被提交到处理器的体系结构状态，直到事务执行成功完成。 在交易执行指令块期间遇到存储指令时，系统确定存储指令是监视存储指令还是非监视存储指令。 如果存储指令是监视的存储指令，则系统执行存储操作，并存储与存储指令相关联的高速缓存行，以便随后检测到来自另一进程的高速缓存行的干扰数据访问。 如果存储指令是不受监视的存储指令，则系统执行存储操作而不存储标记高速缓存行。

公开(公告)号：US07168076B2

公开(公告)日：2007-01-23

申请号：US10194911

申请日：2002-07-12

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F9/00

CPC分类号： G06F9/4843 ,  G06F9/3842 ,  G06F9/3851

摘要： One embodiment of the present invention provides a system that facilitates efficient join operations between a head thread and a speculative thread during speculative program execution, wherein the head thread executes program instructions and the speculative thread executes program instructions in advance of the head thread. The system operates by executing a primary version of a program using the head thread, and by executing a speculative version of the program using the speculative thread. When the head thread reaches a point in the program where the speculative thread began executing, the system performs a join operation between the head thread and the speculative thread. This join operation causes the speculative thread to act as a new head thread by switching from executing the speculative version of the program to executing the primary version of the program. To facilitate this switching operation, the system performs a lookup to determine where the new head thread is to commence executing within the primary version of the program based upon where the speculative thread is currently executing within the speculative version of the program.

摘要翻译： 本发明的一个实施例提供了一种在推测程序执行期间有助于头螺纹和推测螺纹之间的有效连接操作的系统，其中头螺纹执行程序指令，并且推测螺纹在头螺纹之前执行程序指令。 该系统通过使用头部线程执行程序的主要版本，并使用推测性线程执行程序的推测版本来进行操作。 当头线到达推测线程开始执行的程序中的一个点时，系统将在头线程和推测线程之间执行连接操作。 此连接操作通过从执行程序的推测版本切换到执行程序的主要版本而使推测线程充当新的头线程。 为了促进这种切换操作，系统执行查找，以基于推测线程当前在程序的推测版本中执行的位置来确定新的头线程将在程序的主版本内开始执行的位置。