公开(公告)号：US06281716B1

公开(公告)日：2001-08-28

申请号：US09195454

申请日：1998-11-18

申请人： Masaaki Mihara

发明人： Masaaki Mihara

IPC分类号： H03K5153

CPC分类号： H03K5/153 ,  H03K5/2481 ,  H03K17/223 ,  H03K17/302

摘要： A resistance element and an N channel MOS transistor are connected in series between an output terminal of a voltage generation circuit in a flash memory and a line of a ground potential. A constant current is conducted to the MOS transistor, and the potential of the drain of the N channel MOS transistor is compared with a reference potential by a comparator. The voltage conversion factor becomes 1, so that the voltage detection accuracy is improved.

摘要翻译： 电阻元件和N沟道MOS晶体管串联连接在闪存中的电压产生电路的输出端和地电位之间。 将恒定电流传导到MOS晶体管，并且通过比较器将N沟道MOS晶体管的漏极的电位与参考电位进行比较。 电压转换系数为1，提高了电压检测精度。

公开(公告)号：US6147547A

公开(公告)日：2000-11-14

申请号：US172769

申请日：1998-10-15

申请人： Taku Ogura ,  Masaaki Mihara

发明人： Taku Ogura ,  Masaaki Mihara

IPC分类号： H02M3/07 ,  G05F1/10

CPC分类号： H02M3/073 ,  H02M2001/009 ,  H02M2003/071

摘要： Output nodes (Noutn, Noutp) outputting a negative potential (VN) and a positive potential (VPS) respectively are supplied with fixed potentials by reset circuits respectively when unused. Switches (SW2, SW3) conduct when generating the negative potential, while switches (SW1, SW4) conduct when generating the positive potential. Reference potentials for the generated potentials are supplied to internal nodes (N10, N20) through the switches (SW1, SW3) respectively. Poly-diode elements are employed for a voltage generation part, whereby a charge pump circuit capable of generating positive and negative voltages can be implemented without remarkably changing a fabrication method.

摘要翻译： 分别输出负电位（VN）和正电位（VPS）的输出节点（Noutn，Noutp）分别由未使用时由复位电路提供固定电位。 当产生负电位时，开关（SW2，SW3）导通，而开关（SW1，SW4）在产生正电位时导通。 所产生的电位的参考电位分别通过开关（SW1，SW3）提供给内部节点（N10，N20）。 多极二极管元件用于电压产生部分，由此可以实现能够产生正和负电压的电荷泵电路，而不显着地改变制造方法。

公开(公告)号：US5940283A

公开(公告)日：1999-08-17

申请号：US882344

申请日：1997-06-25

申请人： Masaaki Mihara ,  Yoshikazu Miyawaki

发明人： Masaaki Mihara ,  Yoshikazu Miyawaki

IPC分类号： G11C16/06 ,  H02M3/07

CPC分类号： H02M3/073

摘要： A high voltage generating device includes a charge pump generating high voltage by boosting a power supply voltage and supplying it to a load, a timer measuring activation time of the charge pump and outputting a signal after a prescribed time period, an A-D converter converting an output voltage of the charge pump into a digital value in response to the signal and outputting four bit binary data, and a current limiting circuit including four P channel MOS transistors connected in parallel between a power supply node and a drain of an N channel MOS transistor which has a gate receiving the digital value output from the A-D converter.

摘要翻译： 高电压产生装置包括通过升高电源电压并将其提供给负载来产生高电压的电荷泵，定时器测量电荷泵的激活时间并在规定的时间段之后输出信号，AD转换器将输出 电荷泵的电压响应于信号而变为数字值并输出四位二进制数据;以及限流电路，包括并联连接在N沟道MOS晶体管的电源节点和漏极之间的四个P沟道MOS晶体管， 具有从AD转换器输出的数字值的门。

公开(公告)号：US5602778A

公开(公告)日：1997-02-11

申请号：US468393

申请日：1995-06-06

申请人： Tomoshi Futatsuya ,  Masaaki Mihara ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Shinichi Kobayashi ,  Minoru Ohkawa

发明人： Tomoshi Futatsuya ,  Masaaki Mihara ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Shinichi Kobayashi ,  Minoru Ohkawa

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/08 ,  G11C29/00 ,  G11C29/04 ,  G11C11/34

CPC分类号： G11C29/804 ,  G11C16/08 ,  G11C29/82 ,  G11C29/848

摘要： A collective erasure type nonvolatile semiconductor memory device which allows use of redundant structure to word lines is provided. A row address buffer having address converting function simultaneously selects a plurality of physically adjacent word lines from a memory array in programming before erasure. Programming before erasure is effected on the memory cells on the simultaneously selected word lines. Even when physically adjacent word lines are short-circuited between each other, programming high voltage can be transmitted to the defective word lines, as these word lines are selected simultaneously. Therefore, the memory cells on the defective word lines can be programmed before erasure, so that over erasure at the time of collective erasing operation can be prevented. Thus, redundant structure for replacing defecting word lines by spare word lines can be utilized.

摘要翻译： 提供了允许对字线使用冗余结构的集体擦除型非易失性半导体存储器件。 具有地址转换功能的行地址缓冲器在擦除之前在编程中同时从存储器阵列中选择多个物理上相邻的字线。 擦除之前的编程对同时选择的字线上的存储单元进行。 即使当物理上相邻的字线彼此短路时，由于这些字线被同时选择，编程高电压也可被传送到有缺陷的字线。 因此，可以在擦除之前对缺陷字线上的存储单元进行编程，从而可以防止在集体擦除操作时的过度擦除。 因此，可以利用用备用字线代替缺陷字线的冗余结构。

公开(公告)号：US5126968A

公开(公告)日：1992-06-30

申请号：US605707

申请日：1990-10-30

申请人： Takeshi Hamamoto ,  Toshifumi Kobayashi ,  Tadato Yamagata ,  Masaaki Mihara

发明人： Takeshi Hamamoto ,  Toshifumi Kobayashi ,  Tadato Yamagata ,  Masaaki Mihara

IPC分类号： G11C15/04

CPC分类号： G11C15/043 ,  G11C15/04

摘要： A semiconductor memory device comprises a plurality or CAM cells. In a refreshing operation, data of "1" is applied to all of bit lines and inversion bit lines. In the CAM cells storing the data "1", writing of the data "1" onto the bit lines and the inversion bit lines is performed. Then, the data of "0" is applied to all of the bit lines and the inversion bit lines. In the CAM cells storing the data "0", writing of the data "0" onto the bit lines and the inversion bit lines is performed. In a partial writing operation, in the CAM cells to which writing is performed, a first control node is activated, thereby making it possible to write the CAM cells. In the rest of the CAM cells, the first control node is inactivated, thereby making it impossible to write the CAM cells.

摘要翻译： 半导体存储器件包括多个或多个单元。 在刷新操作中，将数据“1”应用于所有位线和反转位线。 在存储数据“1”的CAM单元中，执行数据“1”到位线和反转位线的写入。 然后，将数据“0”应用于所有的位线和反转位线。 在存储数据“0”的CAM单元中，执行数据“0”到位线和反转位线的写入。 在部分写入操作中，在执行写入的CAM单元中，第一控制节点被激活，从而使得可以写入CAM单元。 在其余的CAM单元中，第一控制节点被去激活，从而不可能写入CAM单元。

公开(公告)号：US4998027A

公开(公告)日：1991-03-05

申请号：US491014

申请日：1990-03-09

申请人： Masaaki Mihara ,  Toshifumi Kobayashi

发明人： Masaaki Mihara ,  Toshifumi Kobayashi

IPC分类号： G06F13/362 ,  G06F13/364 ,  H03K17/00

CPC分类号： G06F13/364

摘要： Disclosed is an arbiter circuit for arbitrating a contention between two request signals which simultaneously attain the H (logical high) level indicating a "request". In this arbiter circuit, buffer circuits, having different input logic threshold voltages, are connected to the respective outputs of two three-input NAND gates. The respective outputs of these two buffer circuits, as signals indicating "acknowledgement" or "negative acknowledgement" of the request signals, are derived as final outputs of the arbiter circuit. One of the buffer circuits has an input logic threshold voltage lower than a logic threshold voltage of the two NAND gates, while the other buffer circuit has an input logic threshold voltage set higher than the logic threshold voltage of the NAND gates. Therefore, when the NAND gates output a voltage with the logic level neither the H level nor the L (logical low) level, a signal of the logic level H indicating the "negative acknowledgement" and a signal of the logical level L indicating the "acknowledgement" are reliably outputted from the buffer circuit with the lower input logic threshold voltage and from the other buffer circuit with the higher input logic threshold voltage, respectively. That is, even if two requests occur simultaneously, one of the request signals is rapidly acknowledged.

摘要翻译： 公开了一种用于仲裁同时达到表示“请求”的H（逻辑高）电平的两个请求信号之间的争用的仲裁电路。 在该仲裁器电路中，具有不同输入逻辑阈值电压的缓冲电路连接到两个三输入NAND门的相应输出。 这两个缓冲电路的各自的输出，作为指示请求信号的“确认”或“否定确认”的信号被导出为仲裁器电路的最终输出。 其中一个缓冲电路具有低于两个NAND门的逻辑阈值电压的输入逻辑阈值电压，而另一个缓冲电路的输入逻辑阈值电压设置为高于NAND门的逻辑门限电压。 因此，当NAND门不产生具有H电平和L（逻辑低）电平的逻辑电平的电压时，指示“否定确认”的逻辑电平H的信号和表示“ 确认“能够从具有较低输入逻辑阈值电压的缓冲电路和具有较高输入逻辑阈值电压的另一缓冲电路可靠地输出。 也就是说，即使两个请求同时发生，一个请求信号被快速确认。