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    SEMICONDUCTOR PACKAGE STRUCTURE
    64.
    发明申请
    SEMICONDUCTOR PACKAGE STRUCTURE 有权

    公开(公告)号：US20220278055A1

    公开(公告)日：2022-09-01

    申请号：US17744297

    申请日：2022-05-13

    Applicant: MediaTek Inc.

    Inventor： Tzu-Hung Lin ,  Yung-Chang Lien

    IPC: H01L23/00 ,  H01L23/367 ,  H01L23/16 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065

    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a frame, a redistribution layer, and a first semiconductor die. The substrate has a wiring structure and is surrounded by a molding material. The frame is disposed in the molding material and surrounds the substrate. The redistribution layer is disposed over the substrate and electrically coupled to the wiring structure. The first semiconductor die is disposed over the redistribution layer.

    Semiconductor package structure
    65.
    发明授权
    Semiconductor package structure 有权

    公开(公告)号：US11362044B2

    公开(公告)日：2022-06-14

    申请号：US15930645

    申请日：2020-05-13

    Applicant: MEDIATEK INC.

    Inventor： Tzu-Hung Lin ,  Yung-Chang Lien

    IPC: H01L23/00 ,  H01L23/367 ,  H01L23/16 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065

    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a frame, a redistribution layer, and a first semiconductor die. The substrate has a wiring structure and is surrounded by a molding material. The frame is disposed in the molding material and surrounds the substrate. The redistribution layer is disposed over the substrate and electrically coupled to the wiring structure. The first semiconductor die is disposed over the redistribution layer.

    Semiconductor package structure having an annular frame with truncated corners
    66.
    发明授权
    Semiconductor package structure having an annular frame with truncated corners 有权

    公开(公告)号：US11171113B2

    公开(公告)日：2021-11-09

    申请号：US16563919

    申请日：2019-09-08

    Applicant: MEDIATEK INC.

    Inventor： Chia-Cheng Chang ,  Tzu-Hung Lin ,  I-Hsuan Peng ,  Yi-Jou Lin

    IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L23/367

    Abstract: A semiconductor package structure includes a substrate having a first surface and second surface opposite thereto, a first semiconductor die disposed on the first surface of the substrate, a second semiconductor die disposed on the first surface, a molding material surrounding the first semiconductor die and the second semiconductor die, and an annular frame mounted on the first surface of the substrate. The first semiconductor die and the second semiconductor die are arranged in a side-by-side manner. The first semiconductor die is separated from the second semiconductor die by the molding material. The substrate includes a wiring structure. The first semiconductor die and the second semiconductor die are electrically coupled to the wiring structure. The annular frame surrounds the first semiconductor die and the second semiconductor die. The annular frame includes a retracted region at an outer corner of the annular frame.

    Flip chip package utilizing trace bump trace interconnection
    67.
    发明授权
    Flip chip package utilizing trace bump trace interconnection 有权

    公开(公告)号：US11121108B2

    公开(公告)日：2021-09-14

    申请号：US16888845

    申请日：2020-05-31

    Applicant: MEDIATEK INC.

    Inventor： Tzu-Hung Lin ,  Thomas Matthew Gregorich

    IPC: H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31

    Abstract: A flip chip package includes a substrate having a die attach surface, and a die mounted on the die attach surface with an active surface of the die facing the substrate. The die includes a base, a passivation layer overlying the base, a topmost metal layer overlying the passivation, and a stress buffering layer overlying the topmost metal layer, wherein at least two openings are disposed in the stress buffering layer to expose portions of the topmost metal layer. The die is interconnected to the substrate through a plurality of conductive pillar bumps on the active surface. At least one of the conductive pillar bumps is electrically connected to one of the exposed portions of the topmost metal layer through one of the at least two openings.

    Semiconductor package assembly and method for forming the same
    69.
    发明授权
    Semiconductor package assembly and method for forming the same 有权

    公开(公告)号：US10903198B2

    公开(公告)日：2021-01-26

    申请号：US16674298

    申请日：2019-11-05

    Applicant: MEDIATEK INC.

    Inventor： Chia-Cheng Chang ,  I-Hsuan Peng ,  Tzu-Hung Lin

    IPC: H01L25/18 ,  H01L21/78 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538

    Abstract: A semiconductor package assembly and method for forming the same are provided. The semiconductor package assembly includes a first semiconductor die and a second semiconductor die disposed on a first surface of a substrate. The first semiconductor die includes a peripheral region having a second edge facing the first edge of the second semiconductor die and a third edge opposite to the second edge, a circuit region surrounded by the peripheral region, wherein the circuit region has a fourth edge adjacent to the second edge and a fifth edge adjacent to the third edge. A minimum distance between the second edge and the fourth edge is a first distance, a minimum distance between the third edge and the fifth edge is a second distance, and the first distance is different from the second distance.

    Stacked fan-out package structure
    70.
    发明授权
    Stacked fan-out package structure 有权

    公开(公告)号：US10692789B2

    公开(公告)日：2020-06-23

    申请号：US15968449

    申请日：2018-05-01

    Applicant: MediaTek Inc.

    Inventor： Nai-Wei Liu ,  Tzu-Hung Lin ,  I-Hsuan Peng ,  Ching-Wen Hsiao ,  Wei-Che Huang

    IPC: H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56

    Abstract: A semiconductor package structure is provided. The structure includes a first semiconductor die having a first surface and a second surface opposite thereto. A first molding compound surrounds the first semiconductor die. A first redistribution layer (RDL) structure is disposed on the second surface of the first semiconductor die and laterally extends on the first molding compound. A second semiconductor die is disposed on the first RDL structure and has a first surface and a second surface opposite thereto. A second molding compound surrounds the second semiconductor die. A first protective layer covers a sidewall of the first RDL structure and a sidewall of the first molding compound.

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