公开(公告)号：US20240388717A1

公开(公告)日：2024-11-21

申请号：US18784857

申请日：2024-07-25

Applicant: MEDIATEK INC.

Inventor： Chin-Jung Yang ,  Chun-Kai Huang ,  Ping-Han Lee ,  Tzu-Yun Tseng ,  Tung-Hsing Wu

IPC: H04N19/14 ,  H04N19/12 ,  H04N19/172 ,  H04N19/70 ,  H04N19/85

Abstract: A video encoding apparatus includes a content activity analyzer circuit and a video encoder circuit. The content activity analyzer circuit applies a content activity analysis process to a plurality of frames, and generate a plurality of content activity analysis results, wherein the plurality of frames are derived from a plurality of input frames of the video encoding apparatus. The video encoder circuit performs a video encoding process to generate a bitstream output of the video encoding apparatus. At least one frame is not encoded into the bitstream output according to the plurality of content activity analysis results.

公开(公告)号：US10904577B2

公开(公告)日：2021-01-26

申请号：US16194396

申请日：2018-11-19

Applicant: MEDIATEK INC.

Inventor： Li-Heng Chen ,  Chung-Hua Tsai ,  Tung-Hsing Wu ,  Lien-Fei Chen ,  Yu-Kun Lin ,  Yi-Hsin Huang ,  Han-Liang Chou

IPC: H04N19/184 ,  H04N19/85 ,  H04N19/70

Abstract: A video compression system includes a video encoder and a bitstream processing circuit. The video encoder is hardware that performs hardware video encoding upon frames to generate a first bitstream. The first bitstream is output from an entropy encoding circuit of the video encoder. The bitstream processing circuit performs a bitstream post-processing operation upon the first bitstream to produce a second bitstream that is different from the first bitstream, and outputs the second bitstream as a compression output of the frames.

公开(公告)号：US10805519B2

公开(公告)日：2020-10-13

申请号：US16057830

申请日：2018-08-08

Applicant: MEDIATEK INC.

Inventor： Tsu-Ming Liu ,  Chang-Hung Tsai ,  Tung-Hsing Wu ,  Jia-Ying Lin ,  Li-Heng Chen ,  Han-Liang Chou ,  Chi-Cheng Ju

IPC: H04N5/228 ,  H04N5/232 ,  G06K9/62 ,  H04N19/172 ,  H04N19/124 ,  H04N19/176 ,  H04N5/235 ,  G06N20/00 ,  H04N19/162 ,  H04N19/174 ,  G06N3/04 ,  G06N3/08

Abstract: A perception-based image processing apparatus includes an image analyzing circuit and an application circuit. The image analyzing circuit obtains training data, sets a perception model according to the training data, performs an object detection of at least one frame, and generates an object detection information signal based at least partly on a result of the object detection of said at least one frame. The application circuit operates in response to the object detection information signal.

公开(公告)号：US10523938B2

公开(公告)日：2019-12-31

申请号：US15031262

申请日：2014-10-24

Applicant: MEDIATEK INC.

Inventor： Kun-Bin Lee ,  Tung-Hsing Wu ,  Han-Liang Chou

IPC: H04N19/119 ,  H04N19/174 ,  H04N21/43 ,  H04N19/172 ,  H04N19/463 ,  H04N19/184 ,  H04N19/436 ,  H04N19/44 ,  H04N19/46 ,  H04N5/08

Abstract: An image processing method includes: combining a padding region with a picture, wherein any padding pixel included in the padding region is assigned with a predetermined pixel value; and encoding the picture having the padding region combined therewith. For example, the padding region is directly below a bottom edge of the picture. For another example, all of padding pixels included in the padding region have the same pixel value.

公开(公告)号：US10418002B2

公开(公告)日：2019-09-17

申请号：US15786240

申请日：2017-10-17

Applicant: MEDIATEK INC.

Inventor： Ping Chao ,  Ting-An Lin ,  Tung-Hsing Wu ,  Kung-Tsun Yang ,  Wan-Yu Chen ,  Chuang-Chi Chiou ,  Ping-yao Wang ,  Wei-Gen Wu ,  Hsin-Hao Chung ,  Chih-Ming Wang ,  Han-Liang Chou ,  Chung Hsien Lee ,  Yung-Chang Chang ,  Chi-Cheng Ju

IPC: G09G5/393 ,  G09G5/395 ,  H04N19/423 ,  G09G5/39 ,  H04N19/426 ,  H04N19/39 ,  H04N19/59 ,  G06F13/16 ,  H04N1/32

Abstract: Aspects of the disclosure provide a method for merging compressed access units according to compression rates and/or positions of the respective compressed access units. The method can include receiving a sequence of compressed access units corresponding to a sequence of raw access units partitioned from an image or a video frame and corresponding to a sequence of memory spaces in a frame buffer, determining a merged access unit including at least two consecutive compressed access units based on compression rates and/or positions of the sequence of compressed access units. The merged access unit is to be stored in the frame buffer with a reduced gap between the at least two consecutive compressed access units compared with storing the at least two consecutive compressed access units in corresponding memory spaces in the sequence of memory spaces.

公开(公告)号：US10225561B2

公开(公告)日：2019-03-05

申请号：US15210903

申请日：2016-07-15

Applicant: MEDIATEK INC.

Inventor： Li-Heng Chen ,  Tung-Hsing Wu ,  Han-Liang Chou

IPC: H04N19/136 ,  H04N19/176 ,  H04N19/103

Abstract: A method and apparatus of coding using multiple coding modes with multiple color spaces are provided. For the encoder side, a coding mode is selected from a coding mode group. A corresponding color domain is associated with the coding mode and the corresponding color domain is selected from a color-domain group including at least two different color domains. The current coding unit is then encoded in the corresponding color domain using the coding mode. Furthermore, the syntax of the corresponding color domain is signaled in current coding unit syntaxes. The different color domains may include RGB color domain and YCoCg color domain. According to another method, if the midpoint prediction (MPP) mode is selected, a current block is color transformed into another color domain and the MPP coding process is performed in said another color domain.

公开(公告)号：US10126951B2

公开(公告)日：2018-11-13

申请号：US14905970

申请日：2015-06-16

Applicant: MEDIATEK INC.

Inventor： Kun-Bin Lee ,  Tung-Hsing Wu ,  Yi-Hao Wu

IPC: G06F3/06 ,  G06F5/00 ,  G06F13/16

Abstract: A data processing apparatus includes a storage element and a clock controller. The storage element has storage partitions, including a first storage partition and a second storage partition. The clock controller controls clock driving of the first storage partition and the second storage partition. When a processing circuit is configured to operate in a first condition to process a first data sample with a first bit width, the clock controller enables clock driving of both of the first storage partition and the second storage partition. When the processing circuit is configured to operate in a second condition to process a second data sample with a second bit width, the clock controller enables clock driving of the first storage partition and disables clock driving of the second storage partition.

公开(公告)号：US20180027240A1

公开(公告)日：2018-01-25

申请号：US15653550

申请日：2017-07-19

Applicant: MEDIATEK INC.

Inventor： Yen-Chao Huang ,  Li-Heng Chen ,  Tung-Hsing Wu ,  Chung-Hua Tsai ,  Lien-Fei Chen ,  Han-Liang Chou

IPC: H04N19/159 ,  H04N19/50 ,  H04N19/176 ,  H04N19/61

CPC classification number: H04N19/159 ,  H04N19/174 ,  H04N19/176 ,  H04N19/436 ,  H04N19/50 ,  H04N19/61 ,  H04N19/91

Abstract: A video encoding apparatus has a bitstream buffer and a first video encoder. The first video encoder sequentially encodes coding blocks of a first video frame segment in a first encoding order, and outputs encoded data of the coding blocks of the first video frame segment to the bitstream buffer. The first video frame segment is partitioned into a plurality of column tiles, each having at least one tile. The first encoding order is identical to an encoding order of encoding a video frame segment with only a single column tile.

公开(公告)号：US20170230691A1

公开(公告)日：2017-08-10

申请号：US15422484

申请日：2017-02-02

Applicant: MEDIATEK INC.

Inventor： Tung-Hsing Wu ,  Li-Heng Chen ,  Han-Liang Chou

IPC: H04N19/91 ,  H04N19/182 ,  H04N19/50

CPC classification number: H04N19/91

Abstract: An entropy encoder includes an entropy encoding circuit and a size determining circuit. The entropy encoding circuit receives symbols of a pixel group, and entropy encodes data derived from the symbols of the pixel group to generate a bitstream segment which is composed of a first bitstream portion and a second bitstream portion. The first bitstream portion contains encoded magnitude data of the symbols of the pixel group, and the second bitstream portion contains encoded sign data of at least a portion of the symbols of the pixel group. The size determining circuit determines a size of a bitstream portion, wherein the bitstream portion comprises at least one of the first bitstream portion and the second bitstream portion.

公开(公告)号：US09699466B2

公开(公告)日：2017-07-04

申请号：US14140967

申请日：2013-12-26

Applicant: MEDIATEK INC.

Inventor： Tung-Hsing Wu ,  Kun-Bin Lee

IPC: H04N19/176 ,  H04N19/103 ,  H04N19/126 ,  H04N19/156

CPC classification number: H04N19/176 ,  H04N19/103 ,  H04N19/126 ,  H04N19/156

Abstract: Methods for determining reference type of each image unit and adjusting the corresponding lambda table of the reference type are disclosed. Embodiments according to the invention are used to improve the quality of video compression or reduce the requirement of memory buffer, memory power or computation power. The reference type is determined based on the encoder system information or image unit information. The frame/slice type structure of a video sequence is adjusted according to the image unit information of encoded frames or together with input frames. By fine-tuning the mode decision process, the coding efficiency can be improved. The mode decision process is modified by adaptively adjusting the lambda table. The lambda table is adaptively determined according to the conventional image unit type (such as Intra coded, predicted or bi-directional predicted type) and the reference type determined.