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123 条记录 (耗时 0.053 秒)

    Memory system for synchronous data transmission
    65.
    发明授权
    Memory system for synchronous data transmission 有权
    用于同步数据传输的内存系统

    公开(公告)号：US08762675B2

    公开(公告)日：2014-06-24

    申请号：US13620199

    申请日：2012-09-14

    申请人： David T. Wang ,  Suresh Natarajan Rajan

    发明人： David T. Wang ,  Suresh Natarajan Rajan

    IPC分类号： G06F13/28 ,  G06F13/16 ,  G11C7/22

    CPC分类号： G06F13/1689 ,  G06F1/12 ,  G11C7/22

    摘要： One embodiment of the present invention sets forth an interface circuit configured to combine time staggered data bursts returned by multiple memory devices into a larger contiguous data burst. As a result, an accurate timing reference for data transmission that retains the use of data (DQ) and data strobe (DQS) signals in an infrastructure-compatible system while eliminating the cost of the idle cycles required for data bus turnarounds to switch from reading from one memory device to reading from another memory device, or from writing to one memory device to writing to another memory device may be obtained, thereby increasing memory system bandwidth relative to the prior art approaches.

    摘要翻译： 本发明的一个实施例提出了一种接口电路，其被配置为将由多个存储器件返回的时间交错数据突发组合成更大的连续数据脉冲串。 因此，数据传输的准确定时参考保留了在基础架构兼容系统中使用数据（DQ）和数据选通（DQS）信号，同时消除了数据总线周转从读取中切换所需的空闲周期的成本 从一个存储器件到另一个存储器件的读取，或从写入到一个存储器件到另一个存储器件的写入可以获得，从而相对于现有技术的方法增加了存储器系统带宽。

    Emulation of abstracted DIMMs using abstracted DRAMs
    68.
    发明授权
    Emulation of abstracted DIMMs using abstracted DRAMs 有权

    公开(公告)号：US08438328B2

    公开(公告)日：2013-05-07

    申请号：US12378328

    申请日：2009-02-14

    申请人： Michael J. S. Smith ,  Suresh Natarajan Rajan ,  David T. Wang

    发明人： Michael J. S. Smith ,  Suresh Natarajan Rajan ,  David T. Wang

    IPC分类号： G06F12/00

    CPC分类号： G06F13/4239 ,  Y02D10/14 ,  Y02D10/151

    摘要： One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory-related characteristics onto a memory system interface. The characteristics can be presented on the memory system interface via logic signals or protocol exchanges, and the characteristics may include any one or more of, an address space, a protocol, a memory type, a power management rule, a number of pipeline stages, a number of banks, a mapping to physical banks, a number of ranks, a timing characteristic, an address decoding option, a bus turnaround time parameter, an additional signal assertion, a sub-rank, a number of planes, or other memory-related characteristics. Some embodiments include an intelligent register device and/or, an intelligent buffer device. One advantage of the disclosed subsystem is that memory performance may be optimized regardless of the specific protocols used by the underlying memory hardware devices.