公开(公告)号：US20190304533A1

公开(公告)日：2019-10-03

申请号：US16446830

申请日：2019-06-20

Applicant: Micron Technology, Inc.

Inventor： Zhi Qi Huang ,  Wei Lu Chu ,  Hiromasa Noda ,  Dong Pan

IPC: G11C11/4076 ,  G11C11/4072 ,  G11C11/4074

Abstract: A memory device includes a memory array including a plurality of memory cells; and an array timer coupled to the memory array, configured to generate an output timing signal based on a fixed input and a reference signal, wherein: the fixed input is from a supply circuit, the reference signal is from a reference block, and the output timing signal is configured to control the memory array.

公开(公告)号：US20190229955A1

公开(公告)日：2019-07-25

申请号：US16375510

申请日：2019-04-04

Applicant: Micron Technology, Inc.

Inventor： Jun Wu ,  Dong Pan

IPC: H04L25/03 ,  H04L7/00 ,  H04L27/01 ,  G11C7/10

Abstract: A device includes a first terminal configured to receive a reference voltage, a second terminal configured to receive a weighted tap value, a local generator circuit configured to create a group of unsigned voltage correction values based on the reference voltage and the weighted tap value, and a sign configuring circuit configured to receive the group of unsigned voltage correction values from the local generator circuit and assign a polarity to each respective unsigned voltage correction value of the group of unsigned voltage correction values, creating correction signals from the group of unsigned voltage correction values. The device also includes an output configured to transmit the correction signals to a first input of a processing circuit, wherein the processing circuit is configured to use the correction signals to offset inter-symbol interference from a data stream on a distorted bit based at least on a control signal.

公开(公告)号：US10352775B2

公开(公告)日：2019-07-16

申请号：US14866371

申请日：2015-09-25

Applicant: Micron Technology, Inc.

Inventor： Dong Pan

IPC: G01K7/01

Abstract: A temperature sensor is disclosed. The temperature sensor includes an analog core having at least first and second circuit nodes and configured to provide a temperature dependent output, a multiplexer coupled to the first and second circuit nodes and configured for at least first and second states in each of which the first circuit node couples to a different circuit element and in each of which the second circuit node couples to a different circuit element, and a controller coupled to the analog core and configured to provide a temperature measurement that is an average of at least first and second readings of the temperature dependent output of the analog core, the first reading taken while the multiplexer is in the first state, and the second reading taken while the multiplexer is in the second state.

公开(公告)号：US20180375502A1

公开(公告)日：2018-12-27

申请号：US16121237

申请日：2018-09-04

Applicant: Micron Technology, Inc.

Inventor： Dong Pan ,  John D. Porter

IPC: H03K5/007 ,  H03K5/156 ,  H03K17/16

Abstract: An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.

公开(公告)号：US20180294806A1

公开(公告)日：2018-10-11

申请号：US15482020

申请日：2017-04-07

Applicant: Micron Technology, Inc.

Inventor： Dong Pan ,  John D. Porter

IPC: H03K17/16 ,  H03K5/156 ,  H03K5/007

Abstract: An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.

公开(公告)号：US10097169B1

公开(公告)日：2018-10-09

申请号：US15482020

申请日：2017-04-07

Applicant: Micron Technology, Inc.

Inventor： Dong Pan ,  John D. Porter

IPC: H03K5/007 ,  H03K17/16 ,  H03K5/156

Abstract: An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.

公开(公告)号：US20180190368A1

公开(公告)日：2018-07-05

申请号：US15683439

申请日：2017-08-22

Applicant: Micron Technology, Inc.

Inventor： Dong Pan

IPC: G11C29/50 ,  G11C8/06 ,  G06F11/34 ,  G11C8/10 ,  G11C5/14 ,  G06F11/30

CPC classification number: G11C29/50008 ,  G06F11/3037 ,  G06F11/348 ,  G11C5/147 ,  G11C8/06 ,  G11C8/10 ,  G11C8/12 ,  G11C11/401 ,  G11C11/4093 ,  G11C29/025 ,  G11C29/028 ,  G11C2207/105

Abstract: Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resistor, a register storing timing information, and an arbiter circuit configured to determine whether the resistor is available based, at least in part, on the timing information stored in the register. The timing information stored in the register of each respective chip of the plurality of chips is unique to the respective chip among the plurality of chips.

公开(公告)号：US10001793B2

公开(公告)日：2018-06-19

申请号：US14772757

申请日：2015-07-28

Applicant: Micron Technology, Inc.

Inventor： Wei Lu Chu ,  Dong Pan

IPC: G05F3/16 ,  G05F1/46 ,  G05F1/575 ,  G05F1/59

CPC classification number: G05F1/468 ,  G05F1/461 ,  G05F1/575 ,  G05F1/59 ,  G05F3/262 ,  G05F3/30

Abstract: An apparatus is described comprising a bandgap reference circuit comprising: an amplifier including first and second inputs and an output; and a bandgap transistor coupled to the output of the amplifier at a control electrode thereof, the bandgap transistor being further coupled commonly to the first and second inputs of the amplifier at a first electrode thereof to form a feedback path. The apparatus further comprises a resistor coupled to the first electrode of the bandgap transistor.

公开(公告)号：US09767921B1

公开(公告)日：2017-09-19

申请号：US15396259

申请日：2016-12-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dong Pan

IPC: G11C8/10 ,  G06F11/30 ,  G11C29/50 ,  G11C5/14 ,  G11C8/06 ,  G06F11/34

CPC classification number: G11C29/50008 ,  G06F11/3037 ,  G06F11/348 ,  G11C5/147 ,  G11C8/06 ,  G11C8/10 ,  G11C8/12 ,  G11C11/401 ,  G11C11/4093 ,  G11C29/025 ,  G11C29/028 ,  G11C2207/105

Abstract: Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resistor, a register storing timing information, and an arbiter circuit configured to determine whether the resistor is available based, at least in part, on the timing information stored in the register. The timing information stored in the register of each respective chip of the plurality of chips is unique to the respective chip among the plurality of chips.

公开(公告)号：US20170227975A1

公开(公告)日：2017-08-10

申请号：US14772757

申请日：2015-07-28

Applicant: Micron Technology, Inc.

Inventor： Wei Lu Chu ,  Dong Pan

IPC: G05F1/46 ,  G05F1/59 ,  G05F1/575

CPC classification number: G05F1/468 ,  G05F1/461 ,  G05F1/575 ,  G05F1/59 ,  G05F3/30

Abstract: An apparatus is described comprising a bandgap reference circuit comprising: an amplifier including first and second inputs and an output; and a bandgap transistor coupled to the output of the amplifier at a control electrode thereof, the bandgap transistor being further coupled commonly to the first and second inputs of the amplifier at a first electrode thereof to form a feedback path. The apparatus further comprises a resistor coupled to the first electrode of the bandgap transistor.