公开(公告)号：US20230176754A1

公开(公告)日：2023-06-08

申请号：US17544407

申请日：2021-12-07

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Christopher G. Wieduwilt

IPC: G06F3/06

CPC classification number: G06F3/0626 ,  G06F3/0635 ,  G06F3/0679

Abstract: A memory device includes a memory cell array and a set of fuse banks including a common fuse bank storing common bit information corresponding to a plurality of defective memory cells in the memory cell array. The memory device including a plurality of match sub-circuits corresponding to respective defective memory cells of the plurality of defective memory cells. Each match sub-circuit can be configured to provide a determination of whether a memory cell address of a memory cell of the memory cell array matches an address of the respective defective memory cell. The plurality of match sub-circuit can include a shared common bit-processing circuit that is configured to receive common bit-by-bit results of a comparison between a portion of the memory cell address and the common bit information. The common bit-processing circuit can determine whether the common bit information matches the portion of the memory cell address.

公开(公告)号：US11663124B2

公开(公告)日：2023-05-30

申请号：US16800356

申请日：2020-02-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： James S. Rehmeyer ,  Libo Wang ,  Anthony D. Veches ,  Debra M. Bell ,  Di Wu

IPC: G06F11/00 ,  G06F12/06 ,  G06F16/2455 ,  G06F11/10

CPC classification number: G06F12/0646 ,  G06F11/1068 ,  G06F16/24558 ,  G06F2212/70

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, methods, and memories that are capable of performing pattern matching operations within a memory device. The pattern matching operations may be performed on data stored within the memory based on a pattern stored in a register. The result of the pattern matching operation may be provided by the memory. The data may be retrieved from a memory array for the pattern matching operation by a read operation, a refresh operation, an error correction operation, and/or a pattern matching operation. The data may be retrieved from incoming data input lines instead of or in addition to the memory array. How the data is stored or retrieved for pattern matching operations may be controlled by a memory controller.

公开(公告)号：US11610622B2

公开(公告)日：2023-03-21

申请号：US17226975

申请日：2021-04-09

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Nathaniel J. Meier ,  Joo-Sang Lee

IPC: G11C11/00 ,  G11C11/406 ,  H01L25/065

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for staggering the timing of skipped refresh operations on a memory. Memory cells of memories may need to periodically perform refresh operations. In some instances, auto-refresh operations may be periodically skipped when charge retention characteristics of the memory cells of the memory exceed the auto-refresh frequency. To reduce peak current draw during refresh operations, the skipped refresh operations may be staggered across different portions of the memory. In one example, the skipped refresh operation may be staggered in time among memory dies of the memory to limit a number of memory dies that are performing an auto-refresh operation to a maximum number. In another example, the skipped refresh operation may be staggered in time among memory banks of a single memory array to limit a number of memory banks that are performing an auto-refresh operation to a maximum number.

公开(公告)号：US20230074975A1

公开(公告)日：2023-03-09

申请号：US17468523

申请日：2021-09-07

Applicant: Micron Technology, Inc.

Inventor： Christopher G. Wieduwilt ,  James S. Rehmeyer ,  Toshihiko Miyashita

IPC: H01L27/112 ,  G11C17/16 ,  G11C17/18

Abstract: Transistor antifuses are disclosed. An apparatus may include an antifuse that may be configurable either as a short between a first node and a second node or as an open between the first node and the second node. The antifuse may include a selection transistor and an antifuse transistor. A source or drain of the selection transistor may be electrically coupled to the first node. A gate of the selection transistor may be configured to receive a selection voltage. A gate of the antifuse transistor may be electrically coupled the other of the source or drain of the selection transistor. A source or drain of the antifuse transistor may be electrically coupled to the second node. Associated devices, systems, and methods are also disclosed.

公开(公告)号：US11581031B2

公开(公告)日：2023-02-14

申请号：US17338191

申请日：2021-06-03

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

IPC: G11C16/04 ,  G11C11/406 ,  G11C29/00 ,  G11C11/409 ,  G11C11/4074

Abstract: Memory with partial bank refresh is disclosed herein. In one embodiment, a memory system includes a memory controller and a memory device operably connected to the memory controller. The memory device includes (i) a memory array having a memory bank with a plurality of memory cells arranged in a plurality of memory rows and (ii) circuitry. In some embodiments, the circuitry is configured to disable at least one memory row of the memory bank from receiving refresh commands such that memory cells of the at least one memory row are not refreshed during refresh operations of the memory device. In some embodiments, the memory controller is configured to track memory rows that include utilized memory cells and/or to write data to the memory rows in accordance with a programming sequence of the memory device.

公开(公告)号：US20220335993A1

公开(公告)日：2022-10-20

申请号：US17811153

申请日：2022-07-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Di Wu ,  Debra M. Bell ,  Anthony D. Veches ,  James S. Rehmeyer ,  Libo Wang

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/10 ,  G11C11/4096 ,  G11C11/4076

Abstract: Tracking circuitry may be used to determine if commands and/or command sequences include illegal commands and/or illegal command sequences. If the commands and/or command sequences include illegal commands and/or illegal command sequences, the tracking circuitry may activate signals that prevent execution of the commands and/or notice of the detected illegal commands and/or command sequences.

公开(公告)号：US11462254B2

公开(公告)日：2022-10-04

申请号：US17094731

申请日：2020-11-10

Applicant: Micron Technology, Inc.

Inventor： Gary L. Howe ,  Miles S. Wiscombe ,  James S. Rehmeyer ,  Eric J. Stave

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/4074 ,  G11C5/14

Abstract: Methods, apparatuses, and systems related to voltage management of memory apparatuses/systems are described. The memory device can include circuitry configured to determine an operating frequency of a clock signal for an ongoing or an upcoming memory operation. The memory device may generate a control indicator for increasing a system voltage for higher operating frequencies, for decreasing the system voltage for lower operating frequencies, or a combination thereof.

公开(公告)号：US11442940B2

公开(公告)日：2022-09-13

申请号：US16807692

申请日：2020-03-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Debra M. Bell ,  Libo Wang ,  Di Wu ,  James S. Rehmeyer ,  Anthony D. Veches

IPC: G06F16/2455 ,  G11C11/407 ,  G11C11/4096 ,  G11C11/54 ,  G11C7/10

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, methods, and memories that are capable of performing pattern matching operations within a memory device. The pattern matching operations may be performed on data stored within the memory based on a pattern stored in a register. The result of the pattern matching operation may be provided by the memory. The data on which the pattern matching operation is performed may not be output from the memory during the pattern matching operation.

公开(公告)号：US20220148645A1

公开(公告)日：2022-05-12

申请号：US17091969

申请日：2020-11-06

Applicant: Micron Technology, Inc.

Inventor： Nathaniel J. Meier ,  James S. Rehmeyer ,  David R. Brown

IPC: G11C11/406 ,  G06F3/06

Abstract: Methods, apparatuses, and systems related to managing operations performed in response to refresh management (RFM) commands. A controller generates the RFM command for coordinating a refresh management operation targeted for implementation at an apparatus. The apparatus tracks refresh target set that includes refresh management target locations within the apparatus. According to the tracked refresh management target set, the apparatus selectively implements the targeted refresh management operation and/or a response operation in addition to or as a replacement for the targeted refresh management operation.

公开(公告)号：US11200939B1

公开(公告)日：2021-12-14

申请号：US16921729

申请日：2020-07-06

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Jason M. Johnson ,  Joo-Sang Lee

IPC: G11C11/40 ,  G11C11/406 ,  G06F11/30

Abstract: Memory devices, systems, and associated methods with per die temperature-compensated refresh control, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory cells and a sensor configured to measure a temperature of the memory device. The memory device determines a frequency at which it is receiving refresh commands. The memory device is further configured to skip refresh operations of the memory cells based, at least in part, on the determination and on the temperature of the memory device.