公开(公告)号：US20160062673A1

公开(公告)日：2016-03-03

申请号：US14836673

申请日：2015-08-26

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G06F3/06

CPC classification number: G11C7/10 ,  G06F7/00 ,  G06F7/535 ,  G06F9/3001 ,  G06F12/02 ,  G06F12/0207 ,  G11C7/1006

Abstract: Examples of the present disclosure provide apparatuses and methods related to performing division operations in memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a dividend element. An example apparatus might include a second group of memory cells coupled to a second access line and configured to store a divisor element. An example apparatus might also include a controller configured to cause the dividend element to be divided by the divisor element by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line.

Abstract translation: 本公开的示例提供了与在存储器中执行分割操作相关的装置和方法。 示例性设备可以包括耦合到第一接入线路并被配置为存储分红元件的第一组存储器单元。 示例性装置可以包括耦合到第二接入线路并被配置为存储除数元素的第二组存储器单元。 示例性装置还可以包括控制器，其被配置为通过控制感测电路来执行多个操作而不经由输入/输出（I / O）线传送数据，使得除数元素被除数。

公开(公告)号：US20150357047A1

公开(公告)日：2015-12-10

申请号：US14716079

申请日：2015-05-19

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G11C29/12 ,  G06F9/30 ,  G06F9/38 ,  G11C29/14 ,  G11C29/32

CPC classification number: G11C29/1201 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/3877 ,  G06F9/3887 ,  G06F15/785 ,  G11C7/065 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4096 ,  G11C16/10 ,  G11C29/14 ,  G11C29/32 ,  Y02D10/13

Abstract: Examples of the present disclosure provide apparatuses and methods related to performing comparison operations in a memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a first element. An example apparatus might also include a second group of memory cells coupled to a second access line and configured to store a second element. An example apparatus might also include sensing circuitry configured to compare the first element with the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations without transferring data via an input/output (I/O) line.

Abstract translation: 本公开的示例提供了与在存储器中执行比较操作有关的装置和方法。 示例性设备可以包括耦合到第一接入线路并被配置为存储第一元件的第一组存储器单元。 示例性设备还可以包括耦合到第二接入线路并被配置为存储第二元件的第二组存储器单元。 示例性装置还可以包括感测电路，其被配置为通过在不经由输入/输出（I / O）线路传送数据的情况下执行多个AND运算，OR运算，SHIFT运算和INVERT运算来比较第一元件与第二元件。

公开(公告)号：US20230418606A1

公开(公告)日：2023-12-28

申请号：US18202161

申请日：2023-05-25

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G06F9/30 ,  G06F15/78 ,  G06F7/60

CPC classification number: G06F9/3004 ,  G06F9/30021 ,  G06F9/30036 ,  G06F15/7839 ,  G06F7/607 ,  G06F15/7821

Abstract: Examples of the present disclosure provide apparatuses and methods for determining a vector population count in a memory. An example method comprises determining, using sensing circuitry, a vector population count of a number of fixed length elements of a vector stored in a memory array.

公开(公告)号：US11526355B2

公开(公告)日：2022-12-13

申请号：US17339691

申请日：2021-06-04

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G06F9/30 ,  G06F15/78

Abstract: Examples of the present disclosure provide apparatuses and methods for smallest value element or largest value element determination in memory. An example method comprises: storing an elements vector comprising a plurality of elements in a group of memory cells coupled to an access line of an array; performing, using sensing circuitry coupled to the array, a logical operation using a first vector and a second vector as inputs, with a result of the logical operation being stored in the array as a result vector; updating the result vector responsive to performing a plurality of subsequent logical operations using the sensing circuitry; and providing an indication of which of the plurality of elements have one of a smallest value and a largest value.

公开(公告)号：US11205497B2

公开(公告)日：2021-12-21

申请号：US16818694

申请日：2020-03-13

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G11C29/12 ,  G06F15/78 ,  G06F9/38 ,  G11C7/06 ,  G06F9/30 ,  G11C29/14 ,  G11C29/32 ,  G11C16/10 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/4091

Abstract: Examples of the present disclosure provide apparatuses and methods related to performing comparison operations in a memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a first element. An example apparatus might also include a second group of memory cells coupled to a second access line and configured to store a second element. An example apparatus might also include sensing circuitry configured to compare the first element with the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations without transferring data via an input/output (I/O) line.

公开(公告)号：US11029951B2

公开(公告)日：2021-06-08

申请号：US15237085

申请日：2016-08-15

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G06F9/30 ,  G06F15/78

Abstract: Examples of the present disclosure provide apparatuses and methods for smallest value element or largest value element determination in memory. An example method comprises: storing an elements vector comprising a plurality of elements in a group of memory cells coupled to an access line of an array; performing, using sensing circuitry coupled to the array, a logical operation using a first vector and a second vector as inputs, with a result of the logical operation being stored in the array as a result vector; updating the result vector responsive to performing a plurality of subsequent logical operations using the sensing circuitry; and providing an indication of which of the plurality of elements have one of a smallest value and a largest value.

公开(公告)号：US10705798B2

公开(公告)日：2020-07-07

申请号：US16563063

申请日：2019-09-06

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G06F7/523 ,  G06G7/16 ,  G06F7/53 ,  H03K19/17732 ,  G11C7/10 ,  G11C11/4091

Abstract: Examples of the present disclosure provide apparatuses and methods for performing multi-variable bit-length multiplication operations in a memory. An example method comprises performing a multiplication operation on a first vector and a second vector. The first vector includes a number of first elements stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array. The second vector includes a number of second elements stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The example multiplication operation can include performing a number of AND operations, OR operations and SHIFT operations without transferring data via an input/output (I/O) line.

公开(公告)号：US10540144B2

公开(公告)日：2020-01-21

申请号：US16055658

申请日：2018-08-06

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G06F7/535 ,  G11C7/00 ,  G11C7/06 ,  G11C7/10 ,  G11C11/4091 ,  G06F5/01 ,  G11C11/4076

Abstract: Examples of the present disclosure provide apparatuses and methods for performing signed division operations. An apparatus can include a first group of memory cells coupled to a sense line and to a number of first access lines. The apparatus can include a second group of memory cells coupled to the sense line and to a number of second access lines. The apparatus can include a controller configured to operate sensing circuitry to divide a signed dividend element stored in the first group of memory cells by a signed divisor element stored in the second group of memory cells by performing a number of operations.

公开(公告)号：US20190391789A1

公开(公告)日：2019-12-26

申请号：US16563063

申请日：2019-09-06

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G06F7/523 ,  G06G7/16 ,  G06F7/53 ,  H03K19/177 ,  G11C7/10

Abstract: Examples of the present disclosure provide apparatuses and methods for performing multi-variable bit-length multiplication operations in a memory. An example method comprises performing a multiplication operation on a first vector and a second vector. The first vector includes a number of first elements stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array. The second vector includes a number of second elements stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The example multiplication operation can include performing a number of AND operations, OR operations and SHIFT operations without transferring data via an input/output (I/O) line.

公开(公告)号：US10409554B2

公开(公告)日：2019-09-10

申请号：US15898894

申请日：2018-02-19

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G06F7/523 ,  G11C7/10 ,  G11C11/4096

Abstract: Examples of the present disclosure provide apparatuses and methods for performing multiplication operations in a memory. An example method comprises performing a multiplication operation on a first element stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include a number operations performed without transferring data via an input/output (I/O) line.